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參數資料
| 型號： | A8450KLBTR-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數： | 9/17頁 |
| 文件大?。?/td> | 546K |
| 描述： | IC REG QD BUCK/LINEAR 24-SOIC |
| 標準包裝： | 3,000 |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（4） |
| 功能： | 車載 |
| 輸出數： | 4 |
| 電壓/電流 - 輸出 1： | 5.7V，1.2A |
| 電壓/電流 - 輸出 2： | 5V，200mA |
| 電壓/電流 - 輸出 3： | 5V，200mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 是 |
| 電源電壓： | 6 V ~ 45 V |
| 工作溫度： | -40°C ~ 135°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
Automotive Multioutput Voltage Regulator
A8450
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
to 0 V at 50 mA, as shown in figure 4a. The voltage recovers to its
regulated output when the short is removed.
The V5A and V5D regulators track each other during power-on, and
when the device is enabled and ramped up out of disabled mode,
the regulators will start to track when V
REG
reaches approximately
1.8 V. These regulators are guaranteed to track to within 0.5% of
each other under normal operating conditions.
3.3 V and Adjustable Linear Regulators. Two additional
linear regulators, one that outputs at 3.3 V, and another that has a
1.2 V to 3.3 V adjustable output, can be implemented using external
npn pass transistors. The output voltage of the adjustable regulator,
V
OUTVADJ
(V), is set by the values of the output resistors, R1 and
R2 (?. It can be calculated as
V
OUTVADJ
= V
FB
(1+R1 D R2)
where V
FB
(V) is the voltage on the feedback pin, FB.
Additional pins, CL33 and CLADJ, are provided for setting cur-
rent limits. These are used to protect the external pass transis-
tors from a short-to-ground condition. The current limit setting,
I
CL
(mA), is calculated using the formula
I
CL
= V
OC
D R
RCL
where RCL (? is the current-limiting resistor corresponding to
that regulator (R3 for the 3.3 V regulator, and R4 for the adjustable
regulator). When I
CL
is exceeded, the maximum load current through
that regulator is folded back to 40% of I
CL
?0%, as shown in figure
4b. If current limiting is not needed, the CL33 and CLADJ pins
should be shorted to the VREG pin.
Disabled Mode. When the two input signal pins, ENBAT and
ENB, are pulled low, the A8450 enters disabled mode. This is a
sleep mode, in which all internal circuitry is disabled in order to
draw a minimal current from VBB. When either of these pins is
pulled high, the device is enabled. When emerging from disabled
mode, the buck converter switching regulator does not operate
until the charge pump has stabilized (H 300 約).
Enabled Mode. When one or both of the signal input pins,
ENBAT and ENB, are in the high state, the A8450 is enabled.
ENBAT is an edge-triggered enable (logic 1 e 2.7 V), which is
used to enable the A8450 in response to a high-voltage signal,
such as from an automobile ignition or battery switch. In this
capacity, ENBAT is used only as a momentary switch to wake up
the device. If there is no need for a high-voltage signal, ENBAT
can be pulled low continuously.
ENB is used to initiate the reset of the device. If ENBAT is pulled
6
0
50
100
150
200
250
300
1600
5
4
3
2
1
0
5V Regulators Overcurrent Foldback
I
OUT
(mA)
I
OUTV5DLIM
and I
OUTV5ALIM
Figure 4a. Linear foldback to 50 mA. Foldback occurs at the typical
current limit for the 5 V regulator.
Figure 4b. Linear foldback to a percentage of I
CL
. Foldback occurs at
the current limit setting for the regulator.
6
0
I
CL
1600
5
4
3
2
1
0
3.3 V and Adjustable Regulators Overcurrent Foldback
I
OUT
(mA)
0.4
I
CL
?0%
V
OUTVADJ(min)
V
OUTV33
and V
OUTVADJ(max)
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