參數資料
| 型號： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數： | 1/30頁 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網，PCI，SONET/SDH，無線系統 |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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Revision 1.00/September 2007 Semtech Corp.
Page 1
www.semtech.com
ACS8947T JAM PLL
ADVANCED COMMUNICATIONS
FINAL
Jitter Attenuating, Multiplying Phase-Locked Loop with
Automatic Input Switch and Data Resynchronization Path
ADVANCED COMMS & SENSING
FINAL
DATASHEET
The ACS8947T JAM PLL is a general pupose, Integer N,
jitter-attenuating, differential phase-locked loop for
generating low jitter output clocks. Frequency translation,
reference switching between clock inputs and
resynchronization features are provided also. Typical
application areas include Ethernet, SONET/SDH, PCI, 3G
and wireless systems.
Typical output jitter generation in a SONET/SDH OC-12
system is 2.8 ps RMS, making the ACS8947T an ideal
dejittering solution for use with Semtech clock and line
card parts ACS8510, ACS8520, ACS8525, ACS8522,
ACS8530 and ACS9510.
The ACS8947T has two differential frequency-
programmable LVPECL reference inputs and one
differential synchronization input. The device is capable of
locking across a wide input frequency range of 580 kHz to
180 MHz. Four independently-supplied differential
outputs are available, programmable as LVPECL or CML.
Each output supports a maximum output frequency rate
of up to 625 MHz. All device settings are fully hardwire
configured. An external microprocessor is not required to
program the PLL.
Highly configurable high performance Integer N PLL
with integrated VCO.
VCO frequency range 2.35 GHz to 2.9 GHz.
Configurable closed loop bandwidth from 2 kHz
upwards.
PLL fully configured by hardwired configuration matrix:
no requirement for an external microprocessor.
Full control over internal dividers allows the device to
be configured for a wide range of frequency
translation and jitter cleaning applications.
Meets RMS jitter requirements for OC3 and OC12
telecommunications systems.
Wide input frequency range of 580 kHz to 180 MHz.
Wide output frequency range of 1.23 MHz to
625 MHz.
Input activity monitors and lock detector.
Automatic or manual control of reference selection.
External feedback option.
Wide tracking range of 200 ppm.
Powerful evaluation board and GUI tool for
configuration and device assessment.
3.3 V operation: temperature range - 40°C to +85°C.
Small outline, leadless, 7 mm x 7 mm QFN48
package.
Figure 1 Simplified Block Diagram of the ACS8947T JAM PLL
Block Diagram
Introduction
Features
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