參數資料
| 型號： | AD13280AZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 68CLCC |
| 產品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 80M |
| 數據接口： | 并聯 |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 4.3W |
| 電壓電源： | 模擬和數字，雙 ± |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-CLCC |
| 供應商設備封裝： | 68-CLCC（24.13x24.13） |
| 包裝： | 托盤 |
| 輸入數目和類型： | 2 個差分，雙極 |
| 配用： | AD13280/PCB-ND - KIT EVAL PCB FOR AD13280 |
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Dual-Channel, 12-Bit, 80 MSPS ADC
with Analog Input Signal Conditioning
AD13280
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2002–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Dual 80 MSPS, minimum sample rate
Channel-to-channel matching, ±1% gain error
90 dB channel-to-channel isolation
DC-coupled signal conditioning
80 dB spurious-free dynamic range
Selectable bipolar inputs (±1 V and ±0.5 V ranges)
Integral single-pole, low-pass Nyquist filter
Twos complement output format
3.3 V compatible outputs
1.85 W per channel
APPLICATIONS
Radar processing (optimized for I/Q baseband operation)
Phased array receivers
Multichannel, multimode receivers
GPS antijamming receivers
Communications receivers
PRODUCT HIGHLIGHTS
1.
Guaranteed sample rate of 80 MSPS.
2.
Input signal conditioning; gain and impedance match.
3.
Single-ended, differential, or off-module filter option.
4.
Fully tested/characterized full channel performance.
FUNCTIONAL BLOCK DIAGRAM
TIMING
3
9
12
VREF
DROUT
12
ENCODEA
D9A D10A D11A
(MSB)
D0B
(LSB)
D1B
D3B
D2B
D4B D5B D6B
D7B
D8B
TIMING
D9B
7
5
ENCODEB
B–IN
D10B
D11B (MSB)
D0A (LSB)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
AD13280
DROUTA
AMP-IN-B-2
AMP-IN-B-1
AMP-IN-A-2
AMP-IN-A-1
AMP-OUT-A
A–IN
A+IN
B+IN
AMP-OUT-B
DROUTB
VREF
DROUT
100 OUTPUT TERMINATORS
02
38
6-
00
1
Figure 1.
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