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| 型號： | AD7621ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MO-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大小： | 265K |
| 代理商： | AD7621ASTRL |
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–3–
Parameter
Conditions
Min
Typ
Max
Unit
DIGITAL
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL
Data Format
Pipeline Delay
INPUTS
–0.3
+1.7
– 1
– 1
+0.6
5.25
+ 1
+ 1
V
V
μ A
μ A
OUTPUTS
Parallel or Serial 16-Bits
Conversion Results Available Immediately
After Completed Conversion
I
SINK
= 500 μA
I
SOURCE
= –500 μA
OVDD – 0.3
V
OL
V
OH
0.4
V
V
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current
4
AVDD
DVDD
5
OVDD
5
Power Dissipation
5
2.37
2.37
2.3
2.5
2.5
2.63
2.63
3.6
V
V
V
3 MSPS Throughput
15
4.5
130
mA
mA
μA
PDBUF high @ 3 MSPS
4
PDBUF low @ 3 MSPS
4
PDBUF high @ 1.25 MSPS
6
PDBUF low @ 1.25 MSPS
6
In Power-Down Mode
7
100
108
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mW
mW
mW
mW
μW
TEMPERATURE RANGE
8
Specified Performance
T
MIN
to T
MAX
–40
+85
°C
NOTES
1
LSB means Least Significant Bit. With the ±2.5 V input range, one LSB is 76.294 μV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
In warp mode.
5
Tested in parallel reading mode.
6
In impulse mode.
7
With all digital inputs forced to DVDD or DGND respectively.
8
Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 12 AND 13
Convert Pulsewidth
Time Between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read After
Convert (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time (Warp Mode/Normal Mode/Impulse Mode)
RESET Pulsewidth
t
1
t
2
5
333/500/800
ns
ns
Note 1
t
3
t
4
30
263/400/750
ns
ns
t
5
t
6
t
7
t
8
t
9
1
ns
ns
ns
ns
ns
10
263/400/750
70/100/50
10
REFER TO FIGURES 14, 15, AND 16 (Parallel Interface Modes)
CNVST
LOW to Data Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
t
10
263/400/750
ns
t
11
t
12
t
13
20
ns
ns
ns
40
15
2
(–40 C to +85 C, AVDD = DVDD
= 2.5 V, OVDD = 2.3 V to 3.6 V, unless otherwise noted.)
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