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參數(shù)資料
| 型號： | AD7621ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MO-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大小： | 265K |
| 代理商： | AD7621ASTRL |
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
TIMING SPECIFICATIONS (continued)
–4–
Table I. Serial clock timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Warp)
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
0
0
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
0
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
unit
t
18
t
19
t
19
t
20
t
21
t
22
t
23
t
24
t
28
t
28
t
28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REFER TO FIGURES 18 AND 19 (Master Serial Interface Modes)
2
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
3
Internal SCLK Period
Internal SCLK HIGH
3
Internal SCLK LOW
3
SDOUT Valid Setup Time
3
SDOUT Valid Hold Time
3
SCLK Last Edge to SYNC Delay
3
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
3
CNVST
LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t
14
t
15
t
16
t
17
TBD
TBD
TBD
ns
ns
ns
ns
TBD
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
See Table I
TBD
t
30
TBD
ns
REFER TO FIGURES 20 AND 22 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t
31
t
32
t
33
t
34
t
35
t
36
t
37
5
2
TBD
TBD
12.5
5
5
ns
ns
ns
ns
ns
ns
ns
7
NOTES
1
In warp mode only, the maximum time between conversions is 1ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
Symbol
Min
Typ
Max
Unit
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