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參數(shù)資料
| 型號： | AD7641ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2 MSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 324K |
| 代理商： | AD7641ASTRL |
AD7641
Preliminary Technical Data
Rev. Pr E | Page 20 of 24
SCLK
SDOUT
D17
D16
D1
D0
D15
X17
X16
X15
X
1
X0
Y17
Y16
CS
BUSY
SDIN
EXT/INT = 1
INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
t
34
X17
X16
X
1
2
20
RD = 0
18
17
3
4
19
Figure 21. Slave Serial Data Timing for Reading (Read After Convert)
SDOUT
CS
SCLK
D1
D0
X
D17
D16
D15
1
2
3
16
17
18
t
3
t
35
t
36
t
37
t
31
t
32
t
16
CNVST
BUSY
EXT/INT = 1
INVSCLK = 0
RD =0
Figure 22. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
CNVST
CS
SCLK
SDOUT
RDC/SDIN
BUSY
BUSY
DATA
OUT
AD7641
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7641
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
Figure 23. Two AD7641 in a “Daisy-Chain” Configuration
External Clock Data Read During Conversion
Figure 22 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are both low, the
result of the previous conversion can be read. The data is shifted
out, MSB first, with 18 clock pulses and is valid on both rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done,
RDERROR is pulsed high and can be used to interrupt the host
interface to prevent incomplete data reading. There is no “daisy
chain” feature in this mode and RDC/SDIN input should always
be tied either high or low. To reduce performance degradation
due to digital activity, a fast discontinuous clock of TBD is
recommended to ensure that all the bits are read during the first
half of the conversion phase. It is also possible to begin to read
the data after conversion and continue to read the last bits even
after a new conversion has been initiated.
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