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參數資料
| 型號： | AD7641ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2 MSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數： | 5/24頁 |
| 文件大小： | 324K |
| 代理商： | AD7641ASTRL |
Preliminary Technical Data
AD7641
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 2.5 V, OVDD = 2.3 V to 3.6 V, unless otherwise noted.
Parameter
Refer to Figure 13 and Figure 14
Convert Pulse Width
Time Between Conversions (Warp Mode/Normal Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read After
Convert (Warp Mode/Normal Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode)
Acquisition Time (Warp Mode/Normal Mode)
RESET Pulsewidth
Refer to Figure 15, Figure 16, and Figure 17 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
(Warp Mode/Normal Mode)
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
Refer to Figure 19 and Figure 20 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
(Warp Mode/Normal Mode)
SYNC Asserted to SCLK First Edge Delay
3
Internal SCLK Period
3
Internal SCLK HIGH
3
Internal SCLK LOW
3
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
3
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
3
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode)
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 21 and Figure 22 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
Rev. Pr E | Page 5 of 24
Symbol
t
1
t
2
t
3
t
4
Min
5
500/667
Typ
Max
Note 1
30
340/465
Unit
ns
ns
ns
ns
1
t
5
t
6
t
7
t
8
t
9
t
10
10
70/100
10
1
340/465
340/465
ns
ns
ns
ns
ns
ns
t
11
t
12
t
13
t
14
t
15
t
16
t
17
20
2
TBD
40
15
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
5
2
TBD
TBD
12.5
5
5
TBD
7
ns
ns
ns
ns
ns
ns
ns
ns
1
In warp mode only, the maximum time between conversions is 1ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode.
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