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參數(shù)資料
| 型號： | AD7650 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| 中文描述： | 16位1 MSPS的特區(qū)單極型ADC檔 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大小： | 336K |
| 代理商： | AD7650 |
REV. PrA
PRELIMINARY TECHNICAL DATA
–20–
AD7667
decision made during the first half of the conversion
phase. For this reason, it is recommended that when an
external clock is being provided, it is a discontinuous
clock that is toggling only when BUSY is low or, more
importantly, that it does not transition during the latter
half of BUSY high.
E xternal D iscontinuous C lock D ata R ead After C onver-
sion
T hough the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 18 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the result of this conversion can be read while
both
CS
and
RD
are low. T he data is shifted out, MSB first,
with 16 clock pulses and is valid on both rising and falling
edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed
up to 40 MHz which accommodates both slow digital host
interface and the fastest serial reading.
Finally, in this mode only, the AD7667 provides a “daisy-
chain” feature using the RDC/SDIN input pin for cascading
multiple converters together. T his feature is useful for reducing
component count and wiring connections when desired as, for
instance, in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a com-
mon
CNVST
signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT . Hence, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.
CNVST
CS
SCLK
SDOUT
RDC/SDIN
BUSY
BUSY
DATA
OUT
AD7667
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7667
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
Figure 19. Two AD7667s in a “Daisy-Chain” Configuration
E xternal C lock D ata R ead D uring C onversion
Figure 20 shows the detailed timing diagrams of this
method. During a conversion, while both
CS
and
RD
are
both low, the result of the previous conversion can be read.
T he data is shifted out, MSB first, with 16 clock pulses and is
valid on both rising and falling edge of the clock. T he 16
bits have to be read before the current conversion is com-
plete. If that is not done, RDERROR is pulsed high and
can be used to interrupt the host interface to prevent
incomplete data reading. T here is no “ daisy chain”
feature in this mode and RDC /SDIN input should al-
ways be tied either high or low.
T o reduce performance degradation due to digital activity, a
fast discontinuous clock of, at least 25 MHz, when impulse mode is
used, 32 MHz when normal mode is used or 40 MHz when
warp mode is used, is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is
also possible to begin to read the data after conversion and
continue to read the last bits even after a new conversion has
been initiated. T hat allows the use of a slower clock speed like
18 MHz in impulse mode, 21 MHz in normal mode and 26
MHz in warp mode.
MIC ROPROC E SSOR INT E RF AC ING
T he AD7667 is ideally suited for traditional dc measure-
ment applications supporting a microprocessor, and ac signal
processing applications interfacing to a digital signal processor.
T he AD7667 is designed to interface either with a parallel 16-
bit-wide interface or with a general-purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7667 to prevent digital noise from coupling
into the ADC. T he following sections illustrate the use of the
AD7667 with an SPI-equipped microcontroller, the ADSP-
21065L and ADSP-218x signal processors.
SPI Interface (MC 68HC 11)
Figure 21 shows an interface diagram between the AD7667
and an SPI-equipped microcontroller like the MC68HC11. T o
accommodate the slower speed of the microcontroller, the
AD7667 acts as a slave device and data must be read after
conversion. T his mode allows also the “daisy chain” feature.
T he convert command could be initiated in response to
an internal timer interrupt. T he reading of output data,
one byte at a time, if necessary, could be initiated in
response to the end-of-conversion signal (BUSY going
low) using to an interrupt line of the microcontroller. T he
Serial Peripheral Interface (SPI) on the MC 68HC 11 is
configured for master mode (MST R = 1), Clock Polar-
ity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and
SPI Interrupt Enable (SPIE = 1) by writing to the SPI Con-
trol Register (SPCR). T he IRQ is configured for
edge-sensitive-only operation (IRQE = 1 in OPT ION
register).
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參數(shù)描述 |
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| AD7650ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT, 570KSPS CMOS ADC - Bulk |
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