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參數資料
| 型號： | AD7650 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| 中文描述： | 16位1 MSPS的特區單極型ADC檔 |
| 文件頁數： | 4/23頁 |
| 文件大小： | 336K |
| 代理商： | AD7650 |
REV. PrA
PRELIMINARY TECHNICAL DATA
–4–
AD7667
T able I. Serial clock timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period minimum
Internal SCLK Period typical
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup T ime Minimum
SDOUT Valid Hold T ime Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Warp)
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
0
0
3
25
40
12
7
4
2
3
1.5
1.75
2
0
1
17
50
70
22
21
18
4
60
2
2.25
2.5
1
0
17
100
140
50
49
18
30
140
3
3.25
3.5
1
1
17
200
280
100
99
18
89
300
5.25
5.55
5.75
unit
t
18
t
19
t
19
t
20
t
21
t
22
t
23
t
24
t
24
t
24
t
24
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
REFER T O FIGURES 18 AND 20 (Slave Serial Interface Modes)
2
External SCLK Setup T ime
External SCLK Active Edge to SDOUT Delay
SDIN Setup T ime
SDIN Hold T ime
External SCLK Period
External SCLK HIGH
External SCLK LOW
t
31
t
32
t
33
t
34
t
35
t
36
t
37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
NOT ES
1
In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK , and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode. See T able I for serial master read after convert mode.
Specifications subject to change without notice.
Symbol
Min
T yp
M ax
Unit
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