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參數資料
| 型號： | AD7651 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:D38999 Series III; No. of Contacts:4; Connector Shell Size:13; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
| 中文描述： | 16位1 MSPS的特區單極型ADC檔 |
| 文件頁數： | 3/23頁 |
| 文件大小： | 336K |
| 代理商： | AD7651 |
REV. Pr
A
PRELIMINARY TECHNICAL DATA
–3–
AD7667
Parameter
Operating Current
4
AVD D
5
D VD D
5
OVD D
5
Power Dissipation
5
without REF
Conditions
1 MSPS T hroughput
Min
T yp
Max
Unit
TIMING SPECIFICATIONS
Symbol
M in
T yp
M ax
Unit
REFER T O FIGURES 11 AND 12
Convert Pulsewidth
T ime Between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion T ime
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition T ime
RESET Pulsewidth
t
1
t
2
5
1/1.25/1.5
ns
μs
Note 1
t
3
t
4
30
0.75/1/1.25
ns
μs
t
5
t
6
t
7
2
ns
ns
μs
10
0.75/1/1.25
t
8
t
9
250
10
ns
ns
REFER T O FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST
LOW to DAT A Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DAT A Valid to BUSY LOW Delay
Bus Access Request to DAT A Valid
Bus Relinquish T ime
REFER T O FIGURES 16 AND 17 (Master Serial Interface Modes)
2
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
2
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH
3
Internal SCLK LOW
3
SDOUT Valid Setup T ime
3
SDOUT Valid Hold T ime
3
SCLK Last Edge to SYNC Delay
3
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
3
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t
10
0.75/1/1.25
μs
t
11
t
12
t
13
45
ns
ns
ns
40
15
5
t
14
t
15
t
16
t
17
10
10
10
ns
ns
ns
ns
25/275/525
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
3
25
12
7
4
2
3
ns
ns
ns
ns
ns
ns
40
10
10
10
ns
ns
ns
μs
See T able I
t
29
0.75/1/1.25
μs
t
30
25
ns
(–40 C to +85 C, AVDD = DVDD
= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
T BD
T BD
T BD
112
15
mA
mA
μA
mW
μW
μW
mW
mW
μW
1 MSPS T hroughput
100 SPS T hroughput
6
In Power-Down Mode
7
1 MSPS T hroughput
100 SPS T hroughput
6
In Power-Down Mode
7
T BD
Power Dissipation
5
with REF
122
10.015
T BD
T EMPERAT URE RANGE
8
Specified Performance
T
MIN
to T
MAX
–40
+85
°C
NOT ES
1
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 μV.
2
See Definition of Specifications section. T hese specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. T ested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
In warp mode.
5
T ested in parallel reading mode using external reference.
6
In impulse mode with external REF.
7
With all digital inputs forced to DVDD or DGND respect
ively.
8
Contact factory for extended temperature range.
9
T he max should be the minimum of 5.25V and DVDD+0.3 V.
Specifications subject to change without notice.
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