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參數資料
| 型號： | AD7651 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:D38999 Series III; No. of Contacts:4; Connector Shell Size:13; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
| 中文描述： | 16位1 MSPS的特區單極型ADC檔 |
| 文件頁數： | 7/23頁 |
| 文件大小： | 336K |
| 代理商： | AD7651 |
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7667
–7–
state of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC
is active HIGH. When HIGH, SYNC is active LOW.
When SER/
PAR
is LOW, this output is used as Bit 6 of the Parallel Port Data Output
Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to invert the SCLK signal.
It is active in both master and slave mode.
When SER/
PAR
is LOW, this output is used as Bit 7 of the Parallel Port Data Output
Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as either an external
data input or a read mode selection input depending on the state of EX T /
INT
.
When EX T /
INT
is HIGH, RDC/SDIN could be used as a data input to daisy chain the conver-
sion results from two or more ADCs onto a single SDOUT line. T he digital data level on
SDIN is output on DAT A with a delay of 16 SCLK periods after the initiation of the read
sequence.
When EX T /
INT
is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN
is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data can be output on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply than the supply of
the host interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground
When SER/
PAR
is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial data out
put synchronized to SCLK . Conversion results are stored in an on-chip register. T he
AD7667 provides the conversion result, MSB first, from its internal shift register. T he
DAT A format is determined by the logic level of OB/
2C
. In serial mode, when EX T /
INT
is LOW, SDOUT is valid on both edges of SCLK .
In serial mode, when EX T /
INT
is HIGH:
If INVSC L K is L OW, SDOUT is updated on SC L K rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising
edge.
When SER/
PAR
is L OW, this output is used as the Bit 9 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock
input or output, dependent upon the logic state of the EX T /
INT
pin. T he active edge
where the data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/
PAR
is LOW, this output is used as the Bit 10 of the Parallel Port Data Output
Bus.
When SER
/PAR
is HIGH, this output, part of the serial port, is used as a digital output
frame synchronization for use with the internal data clock (EX T /
INT
= Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and
remains HIGH while SDOUT output is valid. When a read sequence is initiated and
INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is
valid.
When SER/
PAR
is LOW, this output is used as the Bit 11 of the Parallel Port Data Output
Bus.
When SER/
PAR
is HIGH and EX T /
INT
is HIGH, this output, part of the serial port,
is used as a incomplete read error flag. In slave mode, when a data read is started and
not complete when the following conversion is complete, the current data is lost and
RDERROR is pulsed high.
Bit 12 to Bit 15 of the Parallel Port Data output bus. T hese pins are always outputs regard
less of the state of SER/
PAR
.
Busy Output. T ransitions HIGH when a conversion is started, and remains HIGH until
the conversion is complete and the data is latched into the on-chip shift register. T he fall
ing edge of BUSY could be used as a data ready clock signal.
Must Be T ied to Digital Ground
Read Data. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
Chip Select. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
CS
is also used to gate the external clock.
15
DAT A[6]
DI/O
or INVSCLK
16
DAT A[7]
DI/O
or RDC/SDIN
17
18
OGND
OVD D
P
P
19
20
21
DVDD
D GND
DAT A[8]
or SDOUT
P
P
D O
22
DAT A[9]
or SCLK
DI/O
23
DAT A[10]
D O
or SYNC
24
DAT A[11]
D O
or RDERROR
25–28
DAT A[12:15]
D O
29
BUSY
D O
30
31
DGND
RD
P
DI
32
CS
DI
Pin No.
Mnemonic
T ype
Description
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