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參數資料
型號: AD7651AST
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit 100 kSPS PulSAR Unipolar ADC with Reference
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: MS-026BBC, LQFP-48
文件頁數: 7/28頁
文件大小: 709K
代理商: AD7651AST
AD7651
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7651 Stress Ratings
1
IN
2
, TEMP
2
,REF, REFBUFIN,
INGND, REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
Digital Inputs
PDREF, PDBUF
3
Internal Power Dissipation
4
Internal Power Dissipation
5
Junction Temperature
Storage Temperature Range
Lead Temperature Range
(Soldering 10 sec)
AVDD + 0.3 V to
AGND – 0.3 V
±0.3 V
–0.3 V to +7 V
±7 V
–0.3 V to +7 V
–0.3 V to DVDD + 0.3 V
±20 mA
700 mW
2.5 W
150°C
–65°C to +150°C
300°C
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
2
See
section.
3
See
section.
4
Specification is for the device in free air:
48-Lead LQFP; θ
JA
= 91°C/W, θ
JC
= 30°C/W
5
Specification is for the device in free air:
48-Lead LFCSP; θ
JA
= 26°C/W.
Analog Input
Voltage Reference Input
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
I
OH
500
μ
A
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF*
*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
02964-0-006
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs C
L
= 10 pF
0.8V
t
DELAY
2V
2V
0.8V
0.8V
2V
t
DELAY
02965-0-007
Figure 3. Voltage Reference Levels for Timing
Rev. 0 | Page 7 of 28
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相關代理商/技術參數
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