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參數(shù)資料
| 型號： | AD7651ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit 100 kSPS PulSAR Unipolar ADC with Reference |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 709K |
| 代理商： | AD7651ASTRL |
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AD7651
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
D
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
AGND
AVDD
NC
BYTESWAP
OB/2C
NC
NC
NC = NO CONNECT
SER/PAR
D0
D1
AD7651
D3/DIVSCLK1
D
D
D
O
O
D
D
D
D
D
D
P
P
R
T
A
I
A
A
N
I
R
R
02965-0-002
D2/DIVSCLK0
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1, 36,
41, 42
2, 44
AVDD
3, 6,
7, 40
4
BYTESWAP
Type
1
P
Description
Analog Power Ground Pin.
AGND
P
Input Analog Power Pin. Nominally 5 V.
No Connect.
NC
DI
Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift
register.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),
these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that
clocks the data output. In other serial modes, these pins are not used.
When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected
on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active
in both master and slave modes.
5
OB/2C
DI
8
SER/PAR
DI
9, 10
D[0:1]
DO
11, 12
D[2:3]or
DIVSCLK[0:1]
DI/O
13
D4 or
EXT/INT
DI/O
14
D5 or
INVSYNC
DI/O
15
D6 or
INVSCLK
DI/O
Rev. 0 | Page 8 of 28
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| AD7651ASTZ | 功能描述:IC ADC 16BIT 100KSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7651ASTZ | 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7651 LQFP48 |
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| AD7652 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| AD7652ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT 500KSPS SAR UNIPOLAR ADC W/ REF - Bulk 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7652 LFSCP-48 |
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