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參數資料
| 型號： | AD7653 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
| 中文描述： | 16位1 MSPS的特區單極型ADC檔 |
| 文件頁數： | 12/23頁 |
| 文件大小： | 336K |
| 代理商： | AD7653 |
REV. PrA
PRELIMINARY TECHNICAL DATA
–12–
AD7667
C IRC UIT INF ORMAT ION
T he AD7667 is a very fast, low power, single supply, pre-
cise 16-bit analog-to-digital converter (ADC ). T he
AD7667 features different modes to optimize performances
according to the applications.
In warp mode, the AD7667 is capable of converting
1,000,000 samples per second (1MSPS).
T he AD7667 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
T he AD7667 can be operated from a single 5 V supply and
be interfaced to either 5 V or 3 V digital logic. It is housed
in either a 48-lead LQFP package or a 48-lead LFCSP that
saves space and allows flexible configurations as either serial or
parallel interface. T he AD7667 is a pin-to-pin compatible
upgrade of the AD7661/64/66.
C ONVE RT E R OPE RAT ION
T he AD7667 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected to a
“dummy” capacitor of the same value as the capacitive DAC
array.
During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SW
A
. All independent switches are connected to the analog
input IN. T hus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
When the
CNVST
input goes low, a conversion phase is initi-
ated. When the conversion phase begins, SW
A
and SW
B
are
opened first. T he capacitor array and the “dummy” capacitor are
then disconnected from the inputs and connected to the REF-
GND input. T herefore, the differential voltage between IN and
INGND captured at the end of the acquisition phase is applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between REFGND or REF, the comparator input varies by
binary-weighted voltage steps (V
REF
/2, V
REF
/4, . . . V
REF
/65536).
T he control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.
Modes of Operation
T he AD7667 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
T he Warp mode allows the fastest conversion rate up to 1
MSPS. However, in this mode, and this mode only, the full
specified accuracy is guaranteed only when the time between
conversion does not exceed 1 ms. If the time between two con-
secutive conversions is longer than 1 ms, for instance, after
power-up, the first conversion result should be ignored. T his
mode makes the AD7667 ideal for applications where both high
accuracy and fast sample rate are required.
T he normal mode is the fastest mode (800 kSPS) without any
limitation about the time between conversions. T his mode
makes the AD7667 ideal for asynchronous applications such as
data acquisition systems, where both high accuracy and fast
sample rate are required.
T he impulse mode, the lowest power dissipation mode, allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 15 μW. T his feature
makes the AD7667 ideal for battery-powered applications.
T ransfer F unctions
Using the OB/
2C
digital input, the AD7667 offers two output
codings: straight binary and two’s complement. T he LSB size is
V
REF
/65536, which is about 38.15 μV. T he ideal transfer charac-
teristic for the AD7667 is shown in Figure 4 and T able I.
000...000
000...001
000...010
111...101
111...110
111...111
A
ANALOG INPUT
V
REF
1.5 LSB
V
REF
1 LSB
1 LSB
0V
0.5 LSB
1 LSB = V
REF
/65536
Figure 4. ADC Ideal Transfer Function
SW
A
COMP
SW
B
IN
REF
REFGND
LSB
MSB
32,768C
INGND
16,384C
4C
2C
C
C
65,536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
Figure 3. ADC Simplified Schematic
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