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參數資料
| 型號： | AD7653 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
| 中文描述： | 16位1 MSPS的特區單極型ADC檔 |
| 文件頁數： | 16/23頁 |
| 文件大小： | 336K |
| 代理商： | AD7653 |
REV. PrA
PRELIMINARY TECHNICAL DATA
–16–
AD7667
F igure T BD
Power Supply
T he AD7667 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. T he OVDD supply
allows direct interface with any logic working between 2.7 V and
DVDD + 0.3 V. T o reduce the number of supplies needed,
the digital core (DVDD) can be supplied through a simple
RC filter from the analog supply as shown in Figure 5. T he
AD7667 is independent of power supply sequencing, once
OVDD does not exceed DVDD by more than 0.3V, and thus
free from supply voltage induced latchup.
POWE R D ISSIPAT ION Vs. T HROUGHPUT
Operating currents are very low during the acquisition phase,
which
allows a significant power saving when the conversion rate
is reduced
as shown in Figure 10. T his power saving depends on
the mode used. In impulse mode, the AD7667 automatically
reduces its power consumption at the end of each conversion
phase. T his feature makes the AD7667 ideal for very low power
battery applications. It should be noted that the digital interface
remains active even during the acquisition phase. T o reduce the
operating digital supply currents even further, the digital inputs
need to be driven
close to the power supply rails (i.e., DVDD or
DGND
) and OVDD should not exceed DVDD by more than
0.3V.
-160
-140
-120
-100
-80
-60
-40
-20
0
1
TO BE
SUPPLIED
Figure 10. Power Dissipation vs. Sample Rate
C ONV E R S ION C ONT R OL
Figure 11 shows the detailed timing diagrams of the conver-
sion process. T he AD7667 is controlled by the signal
CNVST
which initiates conversion. Once initiated, it cannot be
restarted or aborted, even by the power-down input PD, until
the conversion is complete. T he
CNVST
signal operates
independently of
CS
and
RD
signals.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 11. Basic Conversion Timing
In impulse mode, conversions can be automatically initi-
ated. If
CNVST
is held low when BUSY is low, the
AD7667 controls the acquisition phase and then automati-
cally initiates a new conversion. By keeping
CNVST
low,
the AD7667 keeps the conversion process running by itself.
It should be noted that the analog input has to be settled
when BUSY goes low. Also, at power-up,
CNVST
should be brought low once to initiate the conversion pro-
cess. In this mode, the AD7667 could sometimes run
slightly faster then the guaranteed limits in the impulse mode
of 666 kSPS. T his feature does not exist in warp or normal
modes.
t
9
t
8
RESET
DATA
BUSY
CNVST
Figure 12. RESET Timing
Although
CNVST
is a digital signal, it should be de-
signed with special care with fast, clean edges, and levels
with minimum overshoot and undershoot or ringing.
It is a good thing to shield the
CNVST
trace with ground and
also to add a low value serial resistor (i.e., 50 ) termination
close to the output of the component that drives this line.
For applications where the SNR is critical,
CNVST
signal
should have a very low jitter. Some solutions to achieve that is
to use a dedicated oscillator for
CNVST
generation or, at least,
to clock it with a high-frequency low-jitter clock as shown in
Figure 5.
D IGIT A L INT E R F A C E
T he AD7667 has a versatile digital interface; it can be
interfaced with the host system by using either a serial or
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