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參數資料
| 型號： | AD7655ACPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48 |
| 封裝： | 7 X 7 MM, MO-220-VKKD-2, LFCSP-48 |
| 文件頁數： | 15/20頁 |
| 文件大小： | 684K |
| 代理商： | AD7655ACPRL |
REV. 0
AD7655
–15–
Signals
CS
and
RD
control the interface. When at least one of
these signals is high, the interface outputs are in high impedance.
Usually,
CS
allows the selection of each AD7655 in multicircuit
applications and is held low in a single AD7655 design.
RD
is
generally used to enable the conversion result on the data bus.
In parallel mode, signal A/
B
allows the choice of reading either
the output of Channel A or Channel B, whereas in serial mode,
signal A/
B
controls which channel is output first.
t
1
t
3
t
4
t
17
CNVST
BUSY
DATA BUS
CS
=
RD
= 0
t
16
NEW A
OR B
EOC
PREVIOUS CHANNEL A
OR B
PREVIOUS CHANNEL B
OR NEW A
t
10
Figure 10. Master Parallel Data Timing for Reading
(Continuous Read)
DATA BUS
t
18
t
19
BUSY
CS
RD
CURRENT
CONVERSION
Figure 11. Slave Parallel Data Timing for Reading
(Read after Convert)
PREVIOUS
CONVERSION
t
1
t
3
t
18
t
19
t
4
CS
= 0
CNVST
,
RD
BUSY
DATA BUS
EOC
t
13
t
11
t
12
t
10
Figure 12. Slave Parallel Data Timing for Reading
(Read during Convert)
PARALLEL INTERFACE
The AD7655 is configured to use the parallel interface (Figure 10)
when SER/
PAR
is held low. The data can be read either after each
conversion, which is during the next acquisition phase or during
the other channel
’
s conversion, or during the following conversion
as shown, respectively, in Figures 11 and 12. When the data is
read during the conversion, however, it is recommended that it is
read only during the first half of the conversion phase. That avoids
any potential feedthrough between voltage transients on the
digital interface and the most critical analog conversion circuitry.
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 13, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped,
the
LSB is output on D[15:8], and the MSB is output on D[7:0].
By
connecting BYTESWAP to an address line, the 16-bit data can
be read in two bytes on either D[15:8] or D[7:0].
CS
RD
BYTE
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
HI-Z
HI-Z
t
18
t
18
t
19
Figure 13. 8-Bit Parallel Interface
CS
A/
B
RD
HI-Z
CHANNEL A
t
18
DATA BUS
t
20
CHANNEL B
HI-Z
Figure 14. A/
B
Channel Reading
The detailed functionality of A/
B
is explained in Figure 14.
When high, the data from Channel A is available on the data bus.
When low, the data bus now carries output from Channel B.
Note that Channel A can be read immediately after conversion
is done (
EOC
), while Channel B is still in its converting phase.
SERIAL INTERFACE
The AD7655 is configured to use the serial interface when
SER/
PAR
is held high. The AD7655 outputs 32 bits of data,
MSB first, on the SDOUT pin. The order of the channels being
output is controlled by A/
B
. When HIGH, Channel A is output
first; when LOW, Channel B is output first. Unlike in parallel
mode, Channel A data is updated only after Channel B conversion.
This data is synchronized with the 32 clock pulses provided on
the SCLK pin.
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相關代理商/技術參數 |
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| AD7655ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP T/R |
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