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參數資料
| 型號： | AD7655ACPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48 |
| 封裝： | 7 X 7 MM, MO-220-VKKD-2, LFCSP-48 |
| 文件頁數： | 3/20頁 |
| 文件大小： | 684K |
| 代理商： | AD7655ACPRL |
REV. 0
AD7655
–3–
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current
6
AVDD
DVDD
OVDD
Power Dissipation
4.75
4.75
2.25
5
5
5.25
5.25
5.25
5
V
V
V
1 MSPS Throughput
15.5
8.5
100
120
2.6
114
mA
mA
m
A
mW
mW
mW
1 MSPS Throughput
6
20 kSPS Throughput
7
888 kSPS Throughput
7
135
125
TEMPERATURE RANGE
8
Specified Performance
T
MIN
to T
MAX
–
40
+85
∞
C
NOTES
1
LSB means least significant bit. With the 0 V to 5 V input range, one LSB is 76.294
m
V.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
Sample tested during initial release.
5
The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
6
In Normal Mode.
7
In Impulse Mode.
8
Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 8 and 9
Convert Pulsewidth
Time Between Conversions (Normal Mode/Impulse Mode)
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
(Normal Mode/Impulse Mode)
Aperture Delay
End of Conversions to BUSY LOW Delay
Conversion Time (Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
CNVST
LOW to
EOC
HIGH Delay
EOC
HIGH for Channel A Conversion
(Normal Mode/Impulse Mode)
EOC
LOW after Channel A Conversion
EOC
HIGH for Channel B Conversion
Channel Selection Setup Time
Channel Selection Hold Time
t
1
t
2
t
3
t
4
5
2/2.25
ns
m
s
ns
m
s
32
1.75/2
t
5
t
6
t
7
t
8
t
9
t
10
t
11
2
ns
ns
m
s
ns
ns
ns
m
s
10
1.75/2
250
10
30
1/1.25
t
12
t
13
t
14
t
15
45
ns
m
s
ns
ns
0.75
250
30
Refer to Figures 10, 11, 12, 13, and 14 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
A/
B
LOW to Data Valid Delay
t
16
t
17
t
18
t
19
t
20
1.75/2
m
s
ns
ns
ns
ns
14
40
15
40
5
(–40 C to +85 C, V
REF
= 2.5 V, AVDD = AVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
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