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參數資料
| 型號： | AD7655AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | SEPOSEDPAD, MS-026BBC, LQFP-48 |
| 文件頁數： | 17/20頁 |
| 文件大?。?/td> | 684K |
| 代理商： | AD7655AST |
REV. 0
AD7655
–17–
that it can accommodate slow digital hosts because the serial
clock can be slowed down by using DIVSCLK.
In read during conversion mode, the serial clock and data toggle at
appropriate instants, which minimizes potential feedthrough between
digital activity and the critical conversion decisions. The SYNC
signal goes low after the LSB of each channel has been output.
SLAVE SERIAL INTERFACE
External Clock
The AD7655 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/
INT
pin is held high.
In this mode, several methods can be used to read the data. The
external serial clock is gated by
CS
and the data are output when
both
CS
and
RD
are low. Thus, depending on
CS
, the data can
be read after each conversion or during the following conversion.
The external clock can be either a continuous or discontinuous
clock. A discontinuous clock can be either normally high or
normally low when inactive. Figures 17 and 18 show the detailed
timing diagrams of these methods.
While the AD7655 is performing a bit decision, it is important
that voltage transients do not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
of each channel because the AD7655 provides error correction
circuitry that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is low or,
more importantly, that it does not transition during the latter
half of
EOC
high.
CS
SCLK
SDOUT
CH A
D15
BUSY
SDIN
INVSCLK = 0
t
42
t
43
t
44
t
38
t
39
t
23
t
40
t
41
X
1
2
3
30
31
32
33
34
EXT/
INT
= 1
CH B D0
CH B D1
CH A
D13
CH A
D14
X CH A
D14
X CH A
D15
X CH A
D13
X CH A
D14
X CH A
D15
X CH B
D0
X CH B
D1
Y CH A
D14
Y CH A
D15
RD
= 0
A/
B
= 1
EOC
Figure 17. Slave Serial Data Timing for Reading (Read after Convert)
CNVST
SDOUT
SCLK
X
CH A D15
1
2
3
31
32
t
3
t
42
t
43
t
44
t
38
t
39
t
23
BUSY
INVSCLK = 0
CS
EXT/
INT
= 1
CH B D0
CH B D1
CH A D13
CH A D14
RD
= 0
EOC
t
10
t
11
t
13
t
12
A/
B
= 1
Figure 18. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
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