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參數資料
| 型號： | AD7664 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
| 中文描述： | 16位，570 kSPS的的CMOS模數轉換器 |
| 文件頁數： | 6/19頁 |
| 文件大小： | 392K |
| 代理商： | AD7664 |
REV. 0
AD7664
–6–
Pin
No.
Mnemonic
Type
Description
16
DATA[7]
or RDC/SDIN
DI/O
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/
INT
.
When EXT/
INT
is HIGH, RDC/SDIN could be used as a data input to daisy chain the conver-
sion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/
INT
is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the
data can be output on SDOUT only when the conversion is complete.
Input/Output interface Digital Power Ground.
Input/Output interface Digital Power. Nominally at the same supply than the supply of the
host interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground.
When SER/
PAR
is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7664
provides the conversion result, MSB first, from its internal shift register. The DATA format is
determined by the logic level of OB/
2C
. In serial mode, when EXT/
INT
is LOW, SDOUT is
valid on both edges of SCLK.
In serial mode, when EXT/
INT
is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising
edge.
When SER/
PAR
is LOW, this output is used as the Bit 9 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT
pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/
PAR
is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
When SER
/PAR
is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT
= Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
When SER/
PAR
is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH and EXT/
INT
is HIGH, this output, part of the serial port, is used
as a incomplete read error flag. In slave mode, when a data read is started and not complete
when the following conversion is complete, the current data is lost and RDERROR is pulsed
high.
Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless
of the state of SER/
PAR
.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
Must Be Tied to Digital Ground.
Read Data. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
RD
and
CS
are OR’d together internally.
Chip Select. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
RD
and
CS
are OR’d together internally.
Reset Input. When set to a logic HIGH, reset the AD7664. Current conversion if any is aborted.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
17
18
OGND
OVDD
P
P
19
20
21
DVDD
DGND
DATA[8]
or SDOUT
P
P
DO
22
DATA[9]
or SCLK
DI/O
23
DATA[10]
or SYNC
DO
24
DATA[11]
or RDERROR
DO
25–28
DATA[12:15]
DO
29
BUSY
DO
30
31
DGND
RD
P
DI
32
CS
DI
33
34
RESET
PD
DI
DI
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