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參數(shù)資料
型號(hào): AD7665ASTRL
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 570 kSPS CMOS ADC
中文描述: 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: LOW PROFILE, MS-026BBC, QFP-48
文件頁(yè)數(shù): 16/24頁(yè)
文件大小: 348K
代理商: AD7665ASTRL
REV. 0
AD7665
–16–
75
70
65
60
55
50
45
40
35
1 10 100 1000
FREQUENCY
kHz
P
Figure 9. PSRR vs. Frequency
POWER DISSIPATION
In impulse mode, the AD7665 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows a significant power saving when the conversion rate is
reduced as shown in Figure 10. This feature makes the AD7665
ideal for very low-power battery applications.
This does not take into account the power, if any, dissipated by
the input resistive scaler which depends on the input voltage
range used and the analog input voltage even in power-down
mode. There is no power dissipated when the 0 V to 2.5 V is
used or when both the analog input voltage is 0 V and a unipolar
range, 0 to 5 V or 0 to 10 V, is used.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
100000
10000
1000
100
10
1
0.1
1 10 100 1000 10000 100000 1000000
SAMPLING RATE
SPS
P
WARP/NORMAL
IMPULSE
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7665 is controlled by the signal
CNVST
which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST
signal operates independently of
CS
and
RD
signals.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 11. Basic Conversion Timing
In impulse mode, conversions can be automatically initiated. If
CNVST
is held low when BUSY is low, the AD7665 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping
CNVST
low, the AD7665 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up,
CNVST
should be brought low once to initiate the
conversion process. In this mode, the AD7665 could sometimes
run slightly faster then the guaranteed limits in the impulse
mode of 444 kSPS. This feature does not exist in warp or nor-
mal modes.
Although
CNVST
is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing. It is a good thing to shield
the
CNVST
trace with ground and also to add a low value serial
resistor (i.e., 50
V) termination close to the output of the com-
ponent which drives this line.
For applications where the SNR is critical,
CNVST
signal should
have a very low jitter. Some solutions to achieve that is to use a
dedicated oscillator for
CNVST
generation, or at least to clock
it with a high-frequency low-jitter clock as shown in Figure 5.
t
9
t
8
RESET
DATA
BUSY
CNVST
Figure 12. RESET Timing
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