- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373912 > AD7665ASTRL (ANALOG DEVICES INC) 16-Bit, 570 kSPS CMOS ADC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7665ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 570 kSPS CMOS ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | LOW PROFILE, MS-026BBC, QFP-48 |
| 文件頁(yè)數(shù)： | 19/24頁(yè) |
| 文件大?。?/td> | 348K |
| 代理商： | AD7665ASTRL |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)
REV. 0
AD7665
–19–
CS
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
t
34
X15
X14
X
1
2
3
14
15
16
17
18
EXT/
INT
= 1
RD
= 0
Figure 19. Slave Serial Data Timing for Reading (Read After Convert)
In read-during-conversion mode, the serial clock and data toggle
at appropriate instants which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.
SLAVE SERIAL INTERFACE
External Clock
The AD7665 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
INT
pin is
held high. In this mode, several methods can be used to read the
data. The external serial clock is gated by
CS
and the data are
output when both
CS
and
RD
are low. Thus, depending on
CS
,
the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous or
discontinuous clock. A discontinuous clock can be either nor-
mally high or normally low when inactive. Figure 19 and Figure
21 show the detailed timing diagrams of these methods.
While the AD7665 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par-
ticularly important during the second half of the conversion
phase because the AD7665 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is low or,
more importantly, that is does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read After Conversion
Though the maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both
CS
and
RD
are low. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients on
the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7665 provides a “daisy chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing compo-
nent count and wiring connections when desired as, for instance,
in isolated multiconverter applications.
An example of the concatenation of two devices is shown in Fig-
ure 20. Simultaneous sampling is possible by using a common
CNVST
signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift out
the data on SDOUT. Hence, the MSB of the “upstream” con-
verter just follows the LSB of the “downstream” converter on
the next SCLK cycle.
CNVST
CS
SCLK
SDOUT
RDC/SDIN
BUSY
BUSY
DATA
OUT
AD7665
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7665
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
Figure 20. Two AD7665s in a Daisy-Chain Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7669AN | LC2MOS Complete, 8-Bit Analog I/0 Systems |
| AD7569TE | LC2MOS Complete, 8-Bit Analog I/0 Systems |
| AD7569KN | LC2MOS Complete, 8-Bit Analog I/0 Systems |
| AD7569KP | LC2MOS Complete, 8-Bit Analog I/0 Systems |
| AD7569TQ | LC2MOS Complete, 8-Bit Analog I/0 Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7665ASTZ | 功能描述:IC ADC 16BIT CMOS 5V 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7665ASTZ | 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD7665ASTZRL | 功能描述:IC ADC 16BIT CMOS 5V 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁(yè)面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7666 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| AD7666ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:500KSPS, 16-BIT ACD INT. REF, 2.5LSB - Bulk 制造商:Analog Devices 功能描述:16BIT ADC INT REF 7666 LFSCP-48 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。