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參數資料
| 型號： | AD7677AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 1 LSB INL, 1 MSPS Differential ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數： | 4/20頁 |
| 文件大小： | 322K |
| 代理商： | AD7677AST |
REV. 0
AD7677
TIMING SPECIFICATIONS
–4–
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
Time Between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
t
1
t
2
5
1/1.25/1.5
ns
μ
s
Note 1
t
3
t
4
30
0.75/1/1.25
ns
μ
s
t
5
t
6
t
7
2
ns
ns
μ
s
10
0.75/1/1.25
t
8
t
9
250
10
ns
ns
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figures 17 and 18 (Master Serial Interface Modes)
2
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay (Read During Convert)
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
3
Internal SCLK Period
3
Internal SCLK HIGH
3
Internal SCLK LOW
3
SDOUT Valid Setup Time
3
SDOUT Valid Hold Time
3
SCLK Last Edge to SYNC Delay
3
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read After Convert
3
CNVST
LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t
10
0.75/1/1.25
μ
s
t
11
t
12
t
13
45
ns
ns
ns
40
15
5
t
14
t
15
t
16
t
17
10
10
10
ns
ns
ns
ns
25/275/525
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
3
25
12
7
4
2
3
ns
ns
ns
ns
ns
ns
40
10
10
10
ns
ns
ns
See Table I
0.75/1/1.25
μ
s
t
30
25
ns
Refer to Figures 19 and 20 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t
31
t
32
t
33
t
34
t
35
t
36
t
37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
NOTES
1
In warp mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
(–40 C to +85 C, AVDD = DVDD
= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.)
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