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參數(shù)資料
型號(hào)： AD7705BR
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
中文描述： 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： 0.300 INCH, MS-013AA, SOIC-16
文件頁(yè)數(shù)： 8/32頁(yè)
文件大小： 264K
代理商： AD7705BR
AD7705/AD7706
–8–
REV. A
Table II. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V
Filter First
Notch and O/P
Data Rate
Typical Peak-to-Peak Resolution Bits
Gain of
Gain of
4
8
–3dB
Frequency
Gain of
1
Gain of
2
Gain of
16
Gain of
32
Gain of
64
Gain of
128
MCLK IN = 2.4576 MHz
50Hz
60Hz
250Hz
500Hz
MCLK IN = 1 MHz
20Hz
25Hz
100Hz
200Hz
13.1Hz
15.72Hz
65.5Hz
131Hz
16
16
13
10
16
16
13
10
16
16
13
10
16
16
13
10
16
15
13
10
16
14
13
10
15
14
12
10
14
13
12
10
5.24Hz
6.55Hz
26.2Hz
52.4Hz
16
16
13
10
16
16
13
10
16
16
13
10
16
16
13
10
16
15
13
10
16
14
13
10
15
14
12
10
14
13
12
10
OUTPUT NOISE (3 V OPERATION)
Table III shows the AD7705/AD7706 output rms noise for the selectable notch and –3dB frequencies for the part, as selected by
FS0 and FS1 of the Clock Register. The numbers given are for the bipolar input ranges with a V
REF
of +1.225V and a V
DD
= 3 V.
These numbers are typical and are generated at an analog input voltage of 0V with the part used in either buffered or unbuffered
mode. Table II meanwhile shows the output
peak-to-peak
noise for the selectable notch and –3 dB frequencies for the part.
It is im-
portant to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but
on peak-to-peak noise.
The numbers given are for bipolar input ranges with a V
REF
of +1.225 V and for either buffered or unbuffered
mode. These numbers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Regis-
ter set to 0.
Table III. Output RMS Noise vs. Gain and Output Update Rate @ 3 V
Filter First
Notch and O/P
Data Rate
Typical Output RMS Noise in
m
V
Gain of
Gain of
4
8
–3dB
Frequency
Gain of
1
Gain of
2
Gain of
16
Gain of
32
Gain of
64
Gain of
128
MCLK IN = 2.4576 MHz
50Hz
60Hz
250Hz
500Hz
MCLK IN = 1 MHz
20Hz
25Hz
100Hz
200Hz
13.1Hz
15.72Hz
65.5Hz
131Hz
3.8
5.1
50
270
2.4
2.9
25
135
1.5
1.7
14
65
1.3
1.5
9.9
41
1.1
1.2
5.1
22
1.0
1.0
2.6
9.7
0.9
0.9
2.3
5.1
0.9
0.9
2.0
3.3
5.24Hz
6.55Hz
26.2Hz
52.4Hz
3.8
5.1
50
270
2.4
2.9
25
135
1.5
1.7
14
65
1.3
1.5
9.9
41
1.1
1.2
5.1
22
1.0
1.0
2.6
9.7
0.9
0.9
2.3
5.1
0.9
0.9
2.0
3.3
Table IV. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V
Fi
lter First
Notch and O/P
Data Rate
M
CLK IN = 2.4576 MHz
50Hz
60Hz
250Hz
500Hz
MCLK IN = 1 MHz
20Hz
25Hz
100Hz
200Hz
Typical Peak-to-Peak Resolution in Bits
Gain of
Gain of
Gain of
2
4
8
–3dB
Frequency
Gain of
1
Gain of
16
Gain of
32
Gain of
64
Gain of
128
13.1Hz
15.72Hz
65.5Hz
131Hz
16
16
13
10
16
16
13
10
15
15
13
10
15
14
13
10
14
14
12
10
13
13
12
10
13
13
11
10
12
12
11
10
5.24Hz
6.55Hz
26.2Hz
52.4Hz
16
16
13
10
16
16
13
10
15
15
13
10
15
14
13
10
14
14
12
10
13
13
12
10
13
13
11
10
12
12
11
10
相關(guān)PDF資料
PDF描述
AD7705BRU 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs
AD7706 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs
AD7706BN ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
AD7706BR 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs
AD7706BRU 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs
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