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參數(shù)資料
| 型號(hào)： | AD7707BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC |
| 中文描述： | 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | LOW PROFILE, TSSOP-20 |
| 文件頁(yè)數(shù)： | 17/40頁(yè) |
| 文件大小： | 316K |
| 代理商： | AD7707BRU |
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REV. A
AD7707
–17–
Table XIV. Output Update Rates
CLK*
FS2
FS1
FS0
Output Update Rate
–3 dB Filter Cutoff
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
20 Hz
25 Hz
100 Hz
200 Hz
50 Hz
60 Hz
250 Hz
500 Hz
4.054 Hz
4.23 Hz
4.84 Hz
4.96 Hz
10 Hz
10.34 Hz
11.90 Hz
12.2 Hz
5.24 Hz
6.55 Hz
26.2 Hz
52.4 Hz
13.1 Hz
15.7 Hz
65.5 Hz
131 Hz
1.06 Hz
1.11 Hz
1.27 Hz
1.3 Hz
2.62 Hz
2.71 Hz
3.13 Hz
3.2 Hz
*Assumes correct clock frequency on MCLK IN pin with CLKDIV bit set appropriately.
Data Register (RS2, RS1, RS0 = 0, 1, 1)
The Data Register on the part is a 16-bit read-only register that contains the most up-to-date conversion result from the AD7707. If
the Communications Register sets up the part for a write operation to this register, a write operation must actually take place to re-
turn the part to where it is expecting a write operation to the Communications Register. However, the 16 bits of data written to the
part will be ignored by the AD7707.
Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 00Hex
The part contains a Test Register that is used when testing the device. The user is advised not to change the status of any of the bits
in this register from the default (Power-on or
RESET
) status of all 0s as the part will be placed in one of its test modes and will not
operate correctly.
Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 1F4000Hex
The AD7707 contains independent sets of zero-scale registers, one for each of the input channels. Each of these registers is a 24-bit
read/write register; 24 bits of data must be written otherwise no data will be transferred to the register. This register is used in con-
junction with its associated full-scale register to form a register pair. These register pairs are associated with input channel pairs as
outlined in Table VII. While the part is set up to allow access to these registers over the digital interface, the part itself no longer has
access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibra-
tion registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write
to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking the
FSYNC bit in the mode register high before the calibration register operation and taking it low after the operation is complete.
Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 5761ABHex
The AD7707 contains independent sets of full-scale registers, one for each of the input channels. Each of these registers is a 24-bit
read/write register; 24 bits of data must be written otherwise no data will be transferred to the register. This register is used in con-
junction with its associated zero-scale register to form a register pair. These register pairs are associated with input channel pairs as
outlined in Table X. While the part is set up to allow access to these registers over the digital interface, the part itself no longer has
access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibra-
tion registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write
to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking
FSYNC bit in the mode register high before the calibration register operation and taking it low after the operation is complete.
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