- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373914 > AD7708BR (ANALOG DEVICES INC) Shaft; Style: 2 - light; Applicable Model: LE-P / LEL-W PDF資料下載
參數(shù)資料
| 型號： | AD7708BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Shaft; Style: 2 - light; Applicable Model: LE-P / LEL-W |
| 中文描述： | 10-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 19/44頁 |
| 文件大小： | 339K |
| 代理商： | AD7708BR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
REV. 0
AD7708/AD7718
–19–
SIGNAL CHAIN OVERVIEW CHOP DISABLED
(
CHOP
= 1)
With
CHOP
=1 chopping is disabled. With chopping disabled
the available output rates vary from 16.06 Hz (62.26 ms) to
1365.33 Hz (0.73 ms). The range of applicable SF words is from
3 to 255. When switching between channels with chop disabled,
the channel throughput is increased by a factor of two over the
case where chop is enabled. When used in multiplexed applica-
tions operation with chop disabled will offer the best throughput
time when cycling through all channels. The drawback with
chop disabled is that the drift performance is degraded and
calibration is required following a gain change or significant
temperature change. A block diagram of the ADC input
channel with chop disabled is shown in Figure 10. The
signal chain includes a mux, buffer, PGA, sigma-delta modu-
lator, and digital filter. The modulator bit stream is applied to
a Sinc
3
filter. The programming of the Sinc
3
decimation
factor is restricted to an 8-bit register SF, the actual decima-
tion factor is the register value times 8. The decimated output
rate from the Sinc
3
filter (and the ADC conversion rate) will there-
fore be:
f
f
SF
ADC
MOD
×
=
8
where
f
ADC
is the ADC conversion rate,
SF
is the decimal equivalent of the word loaded to the filter
register, valid range is from 3 to 255,
f
MOD
is the modulator sampling rate of 32.768 kHz.
The settling time to a step input is governed by the digital filter.
A synchronized step change will require a settling time of three
times the programmed update rate, a channel change can be
treated as a synchronized step change. An unsynchronized step
change will require four outputs to reflect the new analog input
at its output.
t
f
t
SETTLE
ADC
ADC
=
=
×
3
3
The allowable range for SF is 3 to 255 with a default of 69
(45H). The corresponding conversion rates, conversion times,
and settling times are shown in Table VI. Note that the conver-
sion time increases by 0.245 ms for each increment in SF.
Table VI. ADC Conversion and Settling Times for Various
SF Words with
CHOP
= 1
SF
Word
Data Update Rate
f
ADC
(Hz)
1365.33
60.2
59.36
54.6
49.95
27.13
16.06
Settling Time
t
SETTLE
(ms)
2.20
49.8
50.54
54.93
60
110.6
186.76
03
68
69 (Default)
75
82
151
255
The frequency response of the digital filter H (f) is as follows:
1
8
8
π
3
SF
SF
sin(
f f
/
f f
/
MOD
)
MOD
×
×
×
×
×
×
sin(
)
π
where
f
MOD
= 32,768 Hz,
SF
= value programmed into SF SFR.
The following shows plots of the filter frequency response using
different SF words for output data rates
of 16 Hz to 1.36 kHz.
There are sinc
3
notches at integer multiples of the update rate.
The 3 dB frequency for all value
s
of
S
F obeys the
following
equation:
f
(3
dB
) = 0.262
×
f
ADC
The following plots show frequency response of the AD7708/
AD7718 digital filter for various filter words. The AD7708/
AD7718 are targeted at multiplexed applications. One of the
key requirements in these applications is to optimize the SF
word to obtain the maximum filter rejection at 50 Hz and 60 Hz
while minimizing the channel throughput rate. Figure 12 shows
the AD7708/AD7718 optimized throughput while maximizing
50 Hz and 60 Hz rejection. This is achieved with an SF word of
75. In Figure 13, by using a higher SF word of 151, 50 Hz and
60 Hz rejection can be maximized at 60 dB with a channel
throughput rate of 110 ms. An SF word of 255 gives maximum
rejection at both 50 Hz and 60 Hz but the channel throughput
rate is restricted to 186 ms as shown in Figure 14.
SINC
3
FILTER
MUX
BUF
PGA
-
MOD0
ANALOG
INPUT
DIGITAL
OUTPUT
f
IN
f
MOD
f
ADC
Figure 10. ADC Channel Block Diagram with CHOP Disabled
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7708BRU | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| AD7708 | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| AD7718 | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| AD7718BR | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| AD7718BRU | 8-/10-Channel, Low Voltage, Low Power, ADCs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7708BR-REEL | 功能描述:IC ADC 16BIT R-R 8/10CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7708BR-REEL7 | 功能描述:IC ADC 16BIT R-R 8/10CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7708BRU | 功能描述:IC ADC 16BIT R-R 8/10CH 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7708BRU-REEL | 功能描述:IC ADC 16BIT R-R 8/10CH 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7708BRU-REEL7 | 功能描述:IC ADC 16BIT R-R 8/10CH 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
發(fā)布緊急采購，3分鐘左右您將得到回復。