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參數資料
| 型號： | AD7714ACHIPS-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| 中文描述： | 5-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, UUC24 |
| 封裝： | DIE |
| 文件頁數： | 15/40頁 |
| 文件大?。?/td> | 306K |
| 代理商： | AD7714ACHIPS-3 |
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2
AD7714
REV. C
–15–
CH2
CH1
CH0
AIN(+)
AIN(–)
Type
Calibration Register Pair
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN1
AIN2
AIN3
AIN4
AIN1
AIN3
AIN5
AIN6
AIN6
AIN6
AIN6
AIN6
AIN2
AIN4
AIN6
AIN6
Pseudo Differential
Pseudo Differential
Pseudo Differential
Pseudo Differential
Fully Differential
Fully Differential
Fully Differential
Test Mode
Register Pair 0
Register Pair 1
Register Pair 2
Register Pair 2
Register Pair 0
Register Pair 1
Register Pair 2
Register Pair 2
Mode Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 00Hex
The Mode Register is an eight bit register from which data can either be read or to which data can be written. Table VIII outlines the
bit designations for the Mode Register.
Table VIII. Mode Register
MD2
MD1
MD0
G2
G1
G0
BO
FSYNC
MD2
MD1
MD0
Operating Mode
0
0
0
Normal Mode; this is the normal mode of operation of the device whereby the device is performing nor-
mal conversions. This is the default condition of these bits after Power-On or
RESET
.
Self-Calibration; this activates self-calibration on the channel selected by CH2, CH1 and CH0 of the
Communications Register. This is a one step calibration sequence and when complete the part returns to
Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The
DRDY
output or bit goes high when
calibration is initiated and returns low when this self-calibration is complete and a new valid word is
available in the data register. The zero-scale calibration is performed at the selected gain on internally
shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally-
generated V
REF
/Selected Gain.
Zero-Scale System Calibration; this activates zero scale system calibration on the channel selected by
CH2, CH1 and CH0 of the Communications Register. Calibration is performed at the selected gain on
the input voltage provided at the analog input during this calibration sequence. This input voltage should
remain stable for the duration of the calibration. The
DRDY
output or bit goes high when calibration is
initiated and returns low when this zero-scale calibration is complete and a new valid word is available in
the data register. At the end of the calibration, the part returns to Normal Mode with MD2, MD1 and
MD0 returning to 0, 0, 0.
Full-Scale System Calibration; this activates full-scale system calibration on the selected input channel.
Calibration is performed at the selected gain on the input voltage provided at the analog input during this
calibration sequence. This input voltage should remain stable for the duration of the calibration. Once
again, the
DRDY
output or bit goes high when calibration is initiated and returns low when this full-scale
calibration is complete and a new valid word is available in the data register. At the end of the calibration,
the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0.
0
0
1
0
1
0
0
1
1
Table VII. Channel Selection
CH2–CH0
Channel Select. These three bits select a channel either for conversion or for access to calibration coefficients as
outlined in Table VII. There are three pairs of calibration registers on the part. In fully differential mode, the part
has three input channels so each channel has its own pair of calibration registers. In pseudo-differential mode, the
AD7714 has five input channels with some of the input channel combinations sharing calibration registers. With
CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself. This can be used as
a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the AIN6
input should be connected to an external voltage within the allowable common-mode range for the part. The
Power-On or RESET status of these bits is 1,0,0 selecting the differential pair AIN1 and AIN2.
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