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參數資料
| 型號： | AD7714ACHIPS-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| 中文描述： | 5-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, UUC24 |
| 封裝： | DIE |
| 文件頁數： | 6/40頁 |
| 文件大小： | 306K |
| 代理商： | AD7714ACHIPS-5 |
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Parameter
LOGIC OUTPUTS (Continued))
V
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
D
ata Output Coding
Y Versions
Units
Conditions/Comments
DV
DD
– 0.6
±
10
9
Binary
Offset Binary
V min
μ
A max
pF typ
I
SOURCE
= 100
μ
A with DV
DD
= 3 V. Except for MCLK OUT
12
Unipolar Mode
Bipolar Mode
TRANSDUCER BURNOUT
14
Current
Initial Tolerance
Drift
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
15
Negative Full-Scale Calibration Limit
15
Offset Calibration Limit
Input Span
1
±
10
0.1
μ
A nom
% typ
%/
°
C typ
(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN V max
–(1.05
×
V
REF
)/GAIN V max
0.8
×
V
REF
(2.1
×
V
REF
)/GAIN
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
V min
V max
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage
+2.7 to +3.3 or
+4.75 to +5.25
+2.7 to +5.25
V
V
V
For Specified Performance
For Specified Performance
DV
Voltage
Power Supply Currents
AV
DD
Current
AV
= 3 V or 5V. BST Bit of Filter High Register = 0
17
, CLKDIS = 1
Typically 0.22 mA. BUFFER = 0 V. f
CLK IN
= 1MHz or 2.4576MHz
Typically 0.45 mA. BUFFER = DV
= 1MHz or 2.4576MHz
AV
= 3 V or 5V. BST Bit of Filter High Register = 1
Typically 0.38mA. BUFFER = 0V. f
CLK IN
= 2.4576MHz
Typically 0.8mA. BUFFER = DV
. f
= 2.4576MHz
Digital I/Ps = 0V or DV
DD.
External MCLK IN, CLKDIS = 1
Typically 0.06mA. DV
DD
= 3 V. f
CLK IN
= 1MHz
Typically 0.13mA. DV
DD
= 5V. f
CLK IN
= 1MHz
Typically 0.15mA. DV
DD
= 3 V. f
CLK IN
= 2.4576MHz
Typically 0.3 mA. DV
DD
= 5V. f
CLK IN
= 2.4576MHz
0.28
0.6
mA max
mA max
0.5
1.1
mA max
mA max
DV
DD
Current
18
0.080
0.16
0.18
0.35
See Note 20
mA max
mA max
mA max
mA max
dB typ
Power Supply Rejection
19
Normal-Mode Power Dissipation
18
AV
= DV
= +3 V. Digital I/Ps = 0V or DV
DD
. External MCLK IN
BST Bit of Filter High Register = 0
Typically 0.84mW. BUFFER = 0V. f
CLK IN
= 1MHz. BST Bit = 0
Typically 1.53mW. BUFFER = +3 V. f
CLK IN
= 1MHz. BST Bit = 0
Typically 1.11mW. BUFFER = 0V. f
CLK IN
= 2.4576MHz. BST Bit = 0
Typically 1.9mW. BUFFER = +3 V. f
= 2.4576MHz. BST Bit = 0
AV
= DV
= +5V. Digital I/Ps = 0V or DV
. External MCLK IN
Typically 1.75 mW. BUFFER = 0V. f
CLK IN
= 1MHz. BST Bit = 0
Typically 2.9 mW. BUFFER = +5V. f
CLK IN
= 1MHz. BST Bit = 0
Typically 2.6mW. BUFFER = 0V. f
= 2.4576MHz. BST Bit = 0
Typically 3.75mW. BUFFER = +5V. f
= 2.4576MHz. BST Bit = 0
External MCLK IN = 0 V or DV
DD
. Typically 9
μ
A. V
DD
= +5 V
External MCLK IN = 0 V or DV
DD
. Typically 4
μ
A. V
DD
= +3 V
1.05
2.04
1.35
2.34
mW max
mW max
mW max
mW max
Normal-Mode Power Dissipation
2.1
3.75
3.1
4.75
18
10
mW max
mW max
mW max
mW max
μ
A max
μ
A max
Standby (Power-Down) Current
21
Standby (Power-Down) Current
21
NOTES
Temperature range is as follows: Y Version: –40
°
C to +105
°
C.
2
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.
3
Recalibration at any temperature will remove these drift errors.
4
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
5
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
6
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for
bipolar ranges.
7
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration.
8
These numbers are guaranteed by design and/or characterization.
9
The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
10
The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which
inputs form differential pairs.
11
V
= REF IN(+) – REF IN(–).
12
These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
13
Sample tested at +25
°
C to ensure compliance.
14
See Burnout Current section.
15
After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.
16
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30mV or go more negative than AGND–30mV. The offset calibration
limit applies to both the unipolar zero point and the bipolar zero point.
17
For higher gains (
≥
8) at f
= 2.4576MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.
18
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD
current and power dissipation will vary depending on the crystal or resonator
type (see Clocking and Oscillator Circuit section).
19
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter
notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.
20
PSRR depends on gain.
Gain
1
2
4
AV
DD
= 3 V
86 dB
78 dB
85 dB
AV
DD
= 5 V
90 dB
78 dB
84 dB
8–128
93 dB
91 dB
21
If the external master clock continues to run in standby mode, the standby current increases to 150
μ
A typical with 5 V supplies and 75
μ
A typical with 3.3 V supplies. When using a crystal
or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or
resonator type (see Standby Mode section).
Specifications subject to change without notice.
–6–
AD7714Y
REV. C
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