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參數資料
| 型號： | AD7714AR-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Metal Oxide Varistor (MOV); Voltage Rating AC, Vrms:680Vrms; Voltage Rating DC, Vdc:895VDC; Peak Surge Current (8/20uS), Itm:4500A; Clamping Voltage 8/20us Max :1815V; Capacitance, Cd:140pF; Package/Case:14mm Disc |
| 中文描述： | 5-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | WSOIC-24 |
| 文件頁數： | 3/40頁 |
| 文件大小： | 306K |
| 代理商： | AD7714AR-5 |
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Parameter
STATIC PERFORMANCE
No Missing Codes
A Versions
Units
Conditions/Comments
24
22
18
15
12
See Tables I to IV
±
0.0015
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.2
±
0.003
1
0.6
Bits min
Bits min
Bits min
Bits min
Bits min
Guaranteed by Design. Bipolar Mode. For Filter Notches
≤
60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
≤
60 Hz
Output Noise
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift
3
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Bipolar Zero Error
Bipolar Zero Drift
3
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Positive Full-Scale Error
4
Full-Scale Drift
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Gain Error
6
Gain Drift
3, 7
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
3
ppm of FSR/
°
C typ
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
Typically
±
0.0004%
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Specifications for AIN and REF IN Unless Noted
At DC. Typically 102 dB.
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
AIN for BUFFER = 0 and REF IN
AIN for BUFFER = 0 and REF IN
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
Normal-Mode 50 Hz Rejection
8
Normal-Mode 60 Hz Rejection
8
Common-Mode 50 Hz Rejection
8
Common-Mode 60 Hz Rejection
8
Common-Mode Voltage Range
9
Absolute AIN/REF IN Voltage
9
90
100
100
150
150
AGND to AV
AGND – 30 mV
AV
DD
+ 30 mV
AGND + 50 mV
AV
DD
– 1.5 V
1
7
0 to +V
/GAIN
11
±
V
/GAIN
GAIN
×
f
CLKIN
/64
f
/8
+1.25
dB min
dB min
dB min
dB min
dB min
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
nom
Absolute/Common-Mode AIN Voltage
9
BUFFER = 1
AIN Input Current
8
AIN Sampling Capacitance
8
AIN Differential Voltage Range
10
Unipolar Input Range (B/U Bit of Filter High Register = 1)
Bipolar Input Range (B/U Bit of Filter High Register = 0)
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
±
1% for Specified Performance. Part Functions with
Lower V
REF
AIN Input Sampling Rate, f
S
REF IN(+) – REF IN(–) Voltage
V nom
REF IN Input Sampling Rate, f
S
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
V
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
Data Output Coding
f
CLK IN
/64
±
10
μ
A max
0.4
2.0
V max
V min
0.4
2.5
V max
V min
0.4
DV
DD
– 0.6
±
10
9
Binary
Offset Binary
V max
V min
μ
A max
pF typ
I
SINK
= 100
μ
A Except for MCLK OUT
12
I
SOURCE
= 100
μ
A Except for MCLK OUT
12
Unipolar Mode
Bipolar Mode
NOTES
7
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with
background calibration.
8
These numbers are guaranteed by design and/or characterization.
9
The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
10
The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII
for which inputs form differential pairs.
11
V
REF
= REF IN(+) – REF IN(–).
12
These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
13
Sample tested at +25
°
C to ensure compliance.
14
See Burnout Current section.
AD7714-3–SPECIFICATIONS
(AV
DD
= +3.3V, DV
DD
= +3.3V, REF IN(+) = +1.25V; REFIN(–) = AGND;
f
CLK IN
= 2.4576MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
AD7714
REV. C
–3–
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