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| 型號： | AD7714YN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| 中文描述： | 5-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數： | 25/40頁 |
| 文件大小： | 306K |
| 代理商： | AD7714YN |
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2
AD7714
REV. C
–25–
System-Offset Calibration
System-offset calibration is a variation of both the system cali-
bration and self-calibration. In this case, the zero-scale point is
determined in exactly the same way as a ZS System Calibration.
The system zero-scale point is presented to the AIN inputs of
the converter. This must be applied to the converter before
the calibration step is initiated and remain stable until the step
is complete. Once the system zero scale has been set up, a
System-Offset Calibration is then initiated by writing the appro-
priate values (1, 0, 0) to the MD2, MD1 and MD0 bits of the
Mode Register. The zero-scale system calibration is performed
at the selected gain.
The full-scale calibration is performed in exactly the same way
as an FS Self Calibration. The full-scale calibration conversion
is performed at the selected gain on an internally generated
voltage of V
REF
/Selected Gain. This is a one step calibration
sequence and the time for calibration is 6
×
1/Output Rate. At
this time, the MD2, MD1 and MD0 bits in the Mode Register
return to 0, 0, 0. This gives the earliest indication that the cali-
bration sequence is complete. The
DRDY
line goes high when
calibration is initiated and does not return low until there is a
valid new word in the data register. The duration time from the
calibration command being issued to
DRDY
going low is 9
×
1/
Output Rate. This is made up of 3
×
1/Output Rate for the zero-
scale system calibration, 3
×
1/Output Rate for the full-scale
self-calibration and 3
×
1/Output Rate for a conversion on the
analog input. This conversion on the analog input is on the
same voltage as the zero-scale system calibration and, therefore,
the resultant word in the data register from this conversion
should be a zero-scale reading. If
DRDY
is low before (or goes
low during) the calibration command write to the Mode Regis-
ter, it may take up to one modulator cycle (MCLKIN/128)
before
DRDY
goes high to indicate that calibration is in
progress. Therefore,
DRDY
should be ignored for up to one
modulator cycle after the last bit of the calibration command is
written to the Mode Register.
In the unipolar mode, the system-offset calibration is performed
between the two endpoints of the transfer function; in the bipolar
mode, it is performed between midscale and positive full scale.
Background Calibration
The AD7714 also offers a background calibration mode where
the part interleaves its calibration procedure with its normal
conversion sequence. In the background calibration mode, the
part provides continuous zero-scale self-calibrations; it does not
provide any full-scale calibrations. The zero-scale point used in
determining the calibration coefficients in this mode is exactly
the same as for a ZS Self-Calibration. The background calibra-
tion mode is invoked by writing 1, 0, 1 to the MD2, MD1,
MD0 bits of the Mode Register. When invoked, the back-
ground calibration mode performs a zero-scale self calibration
after every output update and this reduces the output data rate
of the AD7714 by a factor of six. Its advantage is that the part
is continually performing offset calibrations and automatically
updating its zero-scale calibration coefficients. As a result, the
effects of temperature drift, supply sensitivity and time drift on
zero-scale errors are automatically removed. When the back-
ground calibration mode is turned on, the part will remain in
this mode until bits MD2, MD1 and MD0 of the Mode Regis-
ter are changed.
Because the background calibration does not perform full-scale
calibrations, a self-calibration should be performed before plac-
ing the part in background calibration mode. Removal of the
offset drift in this mode leaves gain drift as the only source of
error not removed from the part. The typical gain drift of the
AD7714 with temperature is 0.2ppm/
°
C. The
SYNC
input or
FSYNC bit should not be exercised when the part is in back-
ground calibration mode.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits on
the amount of offset and span which can be accommodated.
The overriding requirement in determining the amount of offset
and gain which can be accommodated by the part is the require-
ment that the positive full-scale calibration limit is
≤
1.05
×
V
REF
/GAIN. This allows the input range to go 5% above the
nominal range. The built-in headroom in the AD7714’s analog
modulator ensures that the part will still operate correctly with a
positive full-scale voltage which is 5% beyond the nominal.
The range of input span in both the unipolar and bipolar modes
has a minimum value of 0.8
×
V
REF
/GAIN and a maximum
value of 2.1
×
V
REF
/GAIN. However, the span (which is the
difference between the bottom of the AD7714’s input range and
the top of its input range) has to take into account the limitation
on the positive full-scale voltage. The amount of offset which
can be accommodated depends on whether the unipolar or
bipolar mode is being used. Once again, the offset has to take
into account the limitation on the positive full-scale voltage. In
unipolar mode, there is considerable flexibility in handling nega-
tive (with respect to AIN(–)) offsets. In both unipolar and bipo-
lar modes, the range of positive offsets which can be handled by
the part depends on the selected span. Therefore, in determin-
ing the limits for system zero-scale and full-scale calibrations,
the user has to ensure that the offset range plus the span range
does exceed 1.05
×
V
REF
/GAIN. This is best illustrated by
looking at a few examples.
If the part is used in unipolar mode with a required span of
0.8
×
V
REF
/GAIN, the offset range the system calibration can
handle is from –1.05
×
V
REF
/GAIN to +0.25
×
V
REF
/GAIN. If
the part is used in unipolar mode with a required span of V
REF
/
GAIN, the offset range the system calibration can handle is
from –1.05
×
V
REF
/GAIN to +0.05
×
V
REF
/GAIN. Similarly, if
the part is used in unipolar mode and required to remove an
offset of 0.2
×
V
REF
/GAIN, the span range the system calibra-
tion can handle is 0.85
×
V
REF
/GAIN.
If the part is used in bipolar mode with a required span of
±
0.4
×
V
REF
/GAIN, then the offset range which the system cali-
bration can handle is from –0.65
×
V
REF
/GAIN to +0.65
×
V
REF
/GAIN. If the part is used in bipolar mode with a required
span of
±
V
REF
/GAIN, the offset range the system calibration can
handle is from –0.05
×
V
REF
/GAIN to +0.05
×
V
REF
/GAIN.
Similarly, if the part is used in bipolar mode and required to
remove an offset of
±
0.2
×
V
REF
/GAIN, the span range the sys-
tem calibration can handle is
0.85
×
V
REF
/GAIN.
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| AD7714YNZ | 功能描述:IC ADC 24BIT SIGMA-DELTA 24-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7714YNZ | 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA |
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| AD7714YR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 1ksps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 1KSPS 24BIT SERL 24SOIC W - Tape and Reel |
| AD7714YR-REEL7 | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 1ksps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 1KSPS 24BIT SERL 24SOIC W - Tape and Reel |
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