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參數(shù)資料
| 型號(hào)： | AD7724AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | Dual CMOS Modulators |
| 中文描述： | 2-CH 1-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大小： | 552K |
| 代理商： | AD7724AST |
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REV. A
AD7724
–7–
TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7724
[FIGURE 1])
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (100...00 to 100...01 in bipolar mode and
000...00 to 000...01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011...10 to
011...11 in bipolar mode and 111...10 to 111...11 in
unipolar mode). The error is expressed in LSBs.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common–mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB)
when operating in the unipolar mode.
Bipolar Offset Error
This is the deviation of the midscale transition (111...11
to 000...00) from the ideal VIN(+) voltage which is (VIN(–)
–0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above minus full scale. The last code transition should occur for
an analog value 1 1/2 LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Signal-to-(Noise + Distortion)
Signal-to-(Noise + Distortion) is the measured signal-to-noise
plus distortion ratio at the output of the ADC. The signal is the
rms magnitude of the fundamental. Noise plus distortion is the
rms sum of all of the nonfundamental signals and harmonics up
to half the Output Data Rate (f
O
/2), excluding dc. Signal-to-
(Noise + Distortion) is dependent on the number of quantiza-
tion levels used in the digitization process; the more levels, the
smaller the quantization noise. The theoretical Signal-to-(Noise
+ Distortion) ratio for a sine wave input is given by
Signal-to-
(
Noise + Distortion) =
(6.02
N +
1.76)
dB
where
N
is the number of bits.
Total Harmonic Distortion
THD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. THD is defined as
THD
=
20 log
(
V
2
2
+
V
3
2
+
V
4
V
1
2
+
V
5
2
+
V
6
2
)
where
V
1
is the rms amplitude of the fundamental and
V
2
,
V
3
,
V
4
,
V
5
and
V
6
are the rms amplitudes of the second through the
sixth harmonic.
Spurious Free Dynamic Range
Spurious free dynamic range is the difference, in dB, between
the peak spurious or harmonic component in the ADC output
spectrum (up to f
O
/2 and excluding dc) and the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the output spectrum of
the FFT. For input signals whose second harmonics occur in
the stop band region of the digital filter, a spur in the noise floor
limits the SFDR.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa
±
nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
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PDF描述 |
|---|---|
| AD7724 | Dual CMOS Modulators |
| AD7725 | 16-Bit 900 kSPS ADC with a Programmable Postprocessor |
| AD7725BS | 16-Bit 900 kSPS ADC with a Programmable Postprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7724AST-REEL | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 30Msps 15-bit Serial 48-Pin LQFP T/R |
| AD7724ASTZ | 功能描述:IC MOD SIGMA-DELTA DUAL 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專(zhuān)用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類(lèi)型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤(pán) |
| AD7724ASTZ-REEL | 功能描述:IC MOD SIGMA-DELTA DUAL 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專(zhuān)用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類(lèi)型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤(pán) |
| AD7725 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:16-Bit 900 kSPS ADC with a Programmable Postprocessor |
| AD7725BS | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 900ksps 16-bit Parallel/Serial 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:16-BIT PROGRAMMABLE SIGMA-DELTA ADC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7725 MQFP44 |
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