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參數資料
| 型號： | AD7729AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Dual Sigma-Delta ADC with Auxiliary DAC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 142K |
| 代理商： | AD7729AR |
AD7729
–7–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Function
15
MCLK
Master Clock Input. MCLK is driven from a 13 MHz crystal. The active levels for MCLK are
determined by the value of DVDD2.
Active Low Reset Signal. This input resets the entire AD7729 chip, resetting the control
registers and clearing the digital filters. The logic input levels (V
INH
and V
INL
) for RESETB
are determined by the value of DVDD2.
13
RESETB
Power Supply
6
5
7
25
24
AVDD1
AVDD2
AGND
DVDD1
DVDD2
Analog Power Supply Connection for the Rx Section and the Bandgap Reference.
Analog Power Supply Connection for the Auxiliary Section.
Analog Ground Connection.
Digital Power Supply Connection.
Digital Power Supply Connection for the Serial Interface Section. This power supply also sets
the threshold voltages for RxON, RESETB and MCLK.
Digital Ground Connection.
23
Analog Signal and Reference
1, 2
3, 4
26
DGND
IRxP, IRxN
QRxP, QRxN
AUXDAC
Differential Analog Input for I Receive Channel.
Differential Analog Input for Q Receive Channel.
Analog Output Voltage from the 10-Bit Auxiliary DAC AUXDAC. This DAC is used for
functions such as Automatic Gain Control (AGC). The DAC possesses a register that is
accessible via the ASPORT or BSPORT. The DAC may be individually powered down.
A bypass capacitor to AGND of 0.1
μ
F is required for the on-chip reference. The capacitor
should be fixed to this pin.
Buffered Reference Output, which has a nominal value of 1.3 V. A bypass capacitor (to
AGND) of 0.1
μ
F is required on this pin.
28
REFCAP
27
REFOUT
Auxiliary Serial Port (ASPORT)
10
ASCLK
Serial Clock used to clock data or control bits to and from the auxiliary serial port (ASPORT).
The frequency of ASCLK is programmable and is equal to the frequency of the master clock
(MCLK) divided by an integer number.
Serial Data Input of ASPORT. Both data and control information are input on this pin.
Input Framing Signal for ASDI Serial Transfers.
Serial Data Output of ASPORT. Both data and control information are output on this pin.
ASDO is in three-state when no information is being transmitted, thereby allowing external
control.
Output Framing Signal for ASDO Serial Transfers.
ASPORT Enable. When ASE is low, the ASPORT is put into three-state thereby allowing
external control of the serial bus.
9
8
20
ASDI
ASDIFS
ASDO
21
22
ASDOFS
ASE
Baseband Serial Port (BSPORT)
16
BSCLK
Output serial clock used to clock data or control bits to and from the baseband serial port
(BSPORT). The frequency of BSCLK is programmable and is equal to the frequency of the
master clock (MCLK) divided by an integer number.
Serial Data Input of BSPORT. Both data and control information are input on this pin.
Input Framing Signal for BSDI Serial Transfers.
Serial Data Output of BSPORT. Both data and control information are output on this pin.
BSDO is in three-state when no information is being transmitted, thereby allowing external
control.
Output Framing Signal for BSDO Serial Transfers.
BSPORT Enable. When BSE is low, the BSPORT is put into three-state thereby allowing
external control of the serial bus.
12
11
17
BSDI
BSDIFS
BSDO
18
19
BSDOFS
BSE
ADCs
14
RxON
Receive Section Power-On Digital Input. The receive section is powered up by taking pin
RxON high. The receive section can alternatively be powered up by programming bit RxON
in baseband control register BCRA. When the powering up/down of the receive section is
being controlled by pin RxON, bit RxON should equal zero. Similarly, when the powering up/
down of the receive section is being controlled by bit RxON, pin RxON should be tied low.
The logic input levels (V
INH
and V
INL
) for RxON are determined by the value of DVDD2.
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