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參數資料
| 型號： | AD7729ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Dual Sigma-Delta ADC with Auxiliary DAC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 142K |
| 代理商： | AD7729ARU |
AD7729
–13–
REV. 0
Table IV. Baseband and Auxiliary Registers
Name
R/W
Address
Reset
Reserved
Reserved
Reserved
IRxOFFSET
QRxOFFSET
Reserved
Reserved
RxDELAY1
RxDELAY2
ARDADDR
BRDADDR
Reserved
AUXDAC
Reserved
Reserved
Reserved
Reserved
Reserved
ACRA
ACRB
BCRA
BCRB
Reserved
Reserved
Reserved
ASCLKRATE
BSCLKRATE
000000 (0)
000001 (1)
000010 (2)
000011 (3)
000100 (4)
000101 (5)
000110 (6)
000111 (7)
001000 (8)
001001 (9)
001010 (10)
001011 (11)
001100 (12)
001101 (13)
001110 (14)
001111 (15)
010000 (16)
010001 (17)
010010 (18)
010011 (19)
010100 (20)
010101 (21)
010110 (22)
010111 (23)
011000 (24)
011001 (25)
011010 (26)
R/W
R/W
BRESET
BRESET
R/W
R/W
R/W
R/W
BRESET
BRESET
SRESET
SRESET
R/W
ARESET
R/W
R/W
R/W
R/W
ARESET
ARESET
BRESET
BRESET
R/W
R/W
SRESET
SRESET
BRESET: can be reset using pin RESETB or bit BRESET.
ARESET: can be reset using pin RESETB or bit ARESET.
SRESET: only the pin RESETB can reset these registers.
Table V. Baseband Control Register A (BCRA)
Bit
BCRA0
Name
MCLKDIV
Function
MCLK Divider. When this bit is
set to 0, the internal MCLK has
the same value as the external
MCLK. When this bit equals 1,
the external MCLK is divided by
2 within the AD7729 so that the
device operates at half the exter-
nal clock frequency.
Selects AutoCal when set to 1
and UserCal when set to 0.
When set to 1, the Rx calibration
operates in external mode i.e.,
the I and Q analog inputs remain
connected to the pins during the
Rx autocalibration routine.
This bit, in conjunction with
RxPOWER1, is used to reduce
the analog current consumption
of the ADCs.
This bit, in conjunction with
RxPOWER0, is used to reduce
the analog current consumption
of the ADCs.
BCRA1
RxAUTOCAL
BCRA2
RxEXTCAL
BCRA3
RxPOWER0
BCRA4
RxPOWER1
BCRA5
BCRA6
Reserved
RxON
Power-on for the receive section
of the AD7729.
Baseband Reset.
BCRA7
BCRA8
BCRA9
BRESET
Reserved
Reserved
Table VI. Power Modes for the ADCs
RxPOWER1
RxPOWER0
AIDD1 Reduction
0
0
1
1
0
1
0
1
Reserved
1/3 (Power Mode 1)
2/5 (Power Mode 2)
Reserved
Bits RxPOWER0 and RxPOWER1 are used to reduce the ana-
log current consumption of the ADCs. The part is specified in
Power Mode 1. In Power Mode 2, the MCLK needs to be less
than 10 MHz. The performance of the part will then be compa-
rable to the performance in Power Mode 1 except that the ADC
current will now be less than 9.5 mA.
Table VII. Receive Section Activation
RxON Pin
RxON Bit
Receive Section
0
0
1
1
0
1
0
1
OFF
ON
ON
ON
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