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參數資料
| 型號： | AD7731 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| 中文描述： | 低噪聲，高吞吐量的24位Σ-Δ模數轉換器 |
| 文件頁數： | 9/44頁 |
| 文件大小： | 411K |
| 代理商： | AD7731 |
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AD7731
–9–
REV. 0
PIN FUNCT ION DE SCRIPT IONS (Continued)
Pin
No.
Pin
Mnemonic
Function
20
RDY
Logic output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a
logic low on this output indicates that a new output word is available from the AD7731 data register. T he
RDY
pin will return high upon completion of a read operation of a full output word. If no data read has
taken place after an output update, the
RDY
line will return high prior to the next output update, remain
high while the update is taking place and return low again. T his gives an indication of when a read operation
should not be initiated to avoid initiating a read from the data register as it is being updated. In calibration
mode,
RDY
goes high when calibration is initiated and returns low to indicate that calibration is complete. A
number of different events on the AD7731 set the
RDY
high and these are outlined in T able X VII.
Serial Data Output with serial data being read from the output shift register on the part. T his output shift
register can contain information from the calibration registers, mode register, status register, filter register or
data register depending on the register selection bits of the Communications Register.
Serial Data Input with serial data being written to the input shift register on the part. Data from this input
shift register is transferred to the calibration registers, mode register, communications register or filter regis-
ter depending on the register selection bits of the Communications Register.
Digital Supply Voltage, +3 V or +5 V nominal.
Ground reference point for digital circuitry.
21
DOUT
22
DIN
23
24
DV
DD
DGND
T E RMINOLOGY
INT E GRAL NONLINE ARIT Y
T his is the maximum deviation of any code from a straight line
passing through theendpointsof thetransfer function. T he end-
points of the transfer function are zero scale (not to be confused
with bipolar zero), apoint 0.5 LSB below thefirst code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
abovethelast codetransition (111 . . . 110 to 111 . . . 111). T he
error is expressed as a percentage of full scale.
POSIT IVE FULL-SCALE E RROR
Positive Full-Scale Error is the deviation of the last code transi-
tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + V
REF
/GAIN – 3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges.
UNIPOLAR OFFSE T E RROR
Unipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
BIPOLAR ZE RO E RROR
T his is the deviation of the midscale transition (0111 . . . 111
to 1000 . . . 000) from the ideal AIN(+) voltage(AIN(–) –
0.5 LSB) when operating in the bipolar mode.
GAIN E RROR
T his is a measure of the span error of the ADC. It is a measure
of the difference between the measured and the ideal span be-
tween any two points in the transfer function. T he two points
used to calculate the gain error are positive full scale and nega-
tive full scale.
BIPOLAR NE GAT IVE FULL-SCALE E RROR
T his is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – V
REF
/GAIN + 0.5 LSB) when operat-
ing in the bipolar mode. Negative full-scale error is a summation
of zero error and gain error.
POSIT IVE FULL-SCALE OVE RRANGE
Positive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages on AIN(+) input greater than
AIN(–) + V
REF
/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modu-
lator or overflowing the digital filter.
NE GAT IVE FULL-SCALE OVE RRANGE
T his is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – V
REF
/GAIN without overloading the
analog modulator or overflowing the digital filter.
OFFSE T CALIBRAT ION RANGE
In the system calibration modes, the AD7731 calibrates its
offset with respect to the analog input. T he Offset Calibration
Range specification defines the range of voltages the AD7731
can accept and still accurately calibrate offset.
FULL-SCALE CALIBRAT ION RANGE
T his is the range of voltages that the AD7731 can accept in the
system calibration mode and still accurately calibrate full scale.
INPUT SPAN
In system calibration schemes, two voltages applied in sequence
to the AD7731’s analog input define the analog input range.
T he input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7731 can
accept and still accurately calibrate gain.
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| AD7731BN | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
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| AD7731EB | Precision, Zero-Drift Instrumentation Amplifier; Package: SO; No of Pins: 16; Temperature Range: 0°C to +70°C |
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| AD7731BN | 功能描述:IC ADC 24BIT SIGMA-DELTA 24-DIP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD7731BNZ | 功能描述:IC ADC 24BIT SIGMA-DELTA 24DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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