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參數資料
型號: AD7731BN
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Low Noise, High Throughput 24-Bit Sigma-Delta ADC
中文描述: 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24
封裝: MS-001, PLASTIC, DIP-24
文件頁數: 38/44頁
文件大小: 411K
代理商: AD7731BN
AD7731
–38–
REV. 0
T he 8X C51 is configured in its Mode 0 serial interface mode.
Its serial interface contains a single data line. As a result, the
DAT A OUT and DAT A IN pins of the AD7731 should be
connected together. T his means that the AD7731 must not be
configured for continuous read operation when interfacing to
the 8X C51. T he serial clock on the 8X C51 idles high between
data transfers and, therefore, the POL input of the AD7731
should be hard-wired to a logic high. T he 8X C51 outputs the
LSB first in a write operation while the AD7731 expects the
MSB first so the data to be transmitted has to be rearranged
before being written to the output serial register. Similarly, the
AD7731 outputs the MSB first during a read operation while
the 8X C51 expects the LSB first. T herefore, the data read into
the serial buffer needs to be rearranged before the correct data
word from the AD7731 is available in the accumulator.
SYNC
RESET
AD7731
POL
DATA OUT
DATA IN
SCLK
CS
P3.0
P3.1
8XC51
DV
DD
Figure 19. AD7731 to 8XC51 Interface
AD7731 to ADSP-2103/ADSP-2105 Interface
Figure 20 shows an interface between the AD7731 and the
ADSP-2105 DSP processor. In the interface shown, the
RDY
bit of the Status Register is again monitored to determine when
the Data Register is updated. T he alternative scheme is to use
an interrupt driven system, in which case the
RDY
output is
connected to the
IRQ2
input of the ADSP-2105. T he
RFS
and
TFS
pins of the ADSP-2105 are configured as active low out-
puts and the ADSP-2105 serial clock line, SCLK , is also config-
ured as an output. T he POL pin of the AD7731 is hard-wired
low. Because the SCLK from the ADSP-2105 is a continuous
clock, the
CS
of the AD7731 must be used to gate off the clock
once the transfer is complete. T he
CS
for the AD7731 is active
when either the
RFS
or
TFS
outputs from the ADSP-2105 are
active. T he serial clock rate on the ADSP-2105 should be lim-
ited to 3 MHz to ensure correct operation with the AD7731.
SYNC
RESET
AD7731
DATA OUT
DATA IN
SCLK
CS
DR
SCLK
ADSP-2105
DV
DD
RFS
TFS
DT
POL
Figure 20. AD7731 to ADSP-2105 Interface
相關PDF資料
PDF描述
AD7731BR Low Noise, High Throughput 24-Bit Sigma-Delta ADC
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