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參數(shù)資料
| 型號(hào)： | AD774BKR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 12-Bit A/D Converters |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 247K |
| 代理商： | AD774BKR |
REV. C
–3–
CONVERTER START TIMING (Figure 1)
J, K, A, B Grades T Grade
Min Typ Max
Parameter
Symbol
Min Typ Max Unit
Conversion Time
8-Bit Cycle (AD674B)
12-Bit Cycle (AD674B) t
C
8-Bit Cycle (AD774B)
12-Bit Cycle (AD774B) t
C
STS Delay from CE
CE Pulsewidth
CS
to CE Setup
CS
Low During CE High
R/
C
to CE Setup
R/
C
LOW During CE High t
HRC
A
0
to CE Setup
A
0
Valid During CE High
t
C
6
9
4
6
8
12
5
7.3
10
15
6
8
200
6
9
4
6
8
12
5
7.3
10
15
6
8
225
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
t
C
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
50
50
50
50
50
0
50
50
50
50
50
50
0
50
t
SAC
t
HAC
READ TIMING—FULL CONTROL MODE (Figure 2)
J, K, A, B Grades T Grade
Min Typ Max Min Typ Max Unit
Parameter
Symbol
Access Time
C
L
= 100 pF
Data Valid After CE Low
t
DD1
t
HD
75
150
75
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
2
20
3
25
2
15
4
Output Float Delay
CS
to CE Setup
R/
C
to CE Setup
A
0
to CE Setup
CS
Valid After CE Low
R/
C
High After CE Low
A
0
Valid After CE Low
t
HL5
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
150
150
50
0
50
0
0
50
50
0
50
0
0
50
NOTES
1
t
is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
2
0
°
C to T
MAX
.
3
At –40
°
C.
4
At –55
°
C.
5
t
is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
Specifications shown in
boldface
are tested on all devices at final electrical test with
worst case supply voltages at T
, 25
°
C, and T
. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
Specifications subject to change without notice.
Parameter
Test Conditions
Min
Max
Unit
LOGIC INPUTS
V
IH
V
IL
I
IH
I
IL
C
IN
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
2.0
–0.5
–10
–10
V
LOGIC
+ 0.5
+0.8
+10
+10
10
V
V
μ
A
μ
A
pF
V
IN
= V
LOGIC
V
IN
= 0 V
LOGIC OUTPUTS
V
OH
V
OL
I
OZ
C
OZ
High Level Output Voltage
Low Level Output Voltage
High-Z Leakage Current
High-Z Output Capacitance
I
OH
= 0.5 mA
I
OL
= 1.6 mA
V
IN
= 0 to V
LOGIC
2.4
V
V
μ
A
pF
0.4
+10
10
–10
DIGITAL SPECIFICATIONS
(For all grades T
MIN
to T
MAX
with V
CC
= +15 V
10% or +12 V 5%, V
LOGIC
= +5 V 10%,
V
EE
= –15 V 10% or –12 V 5%, unless otherwise noted.)
SWITCHING SPECIFICATIONS
(For all grades T
MIN
to T
MAX
with V
CC
= +15 V 10% or +12 V 5%,
V
LOGIC
= +5 V 10%, V
EE
= –15 V 10% or –12 V 5%, unless otherwise noted.)
t
HEC
t
HSC
t
SSC
t
HRC
t
SRC
t
SAC
t
HAC
t
C
t
DSC
CE
CS
R/
C
A
0
STS
DB11
–
DB0
HIGH
IMPEDANCE
Figure 1. Convert Start Timing
t
SSR
CE
CS
R/
C
A
0
STS
DB11
–
DB0
t
HSR
t
HRR
t
HAR
t
HD
t
SAR
t
SRR
HIGH
IMPEDANCE
DATA
VALID
HIGH
IMPEDANCE
t
HL
t
DD
Figure 2. Read Cycle Timing
DB
N
3k
100pF
DB
N
3k
100pF
5V
HIGH-Z TO LOGIC 0
HIGH-Z TO LOGIC 1
High-Z to Logic 1 High-Z to Logic 0
Figure 3a. Load Circuit for Access Time Test
DB
N
3k
100pF
LOGIC 1 TO HIGH-Z
Logic 1 to High-Z Logic 0 to High-Z
Figure 3b. Load Circuit for Output Float Delay Test
DB
N
3k
100pF
5V
LOGIC 0 TO HIGH-Z
AD674B/AD774B
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