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參數資料
| 型號： | AD7778* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC2MOS. High Speed 1-. 4- & 8-Channel 10-Bit ADCs |
| 中文描述： | LC2MOS。高速1 -. 4 - |
| 文件頁數： | 2/12頁 |
| 文件大?。?/td> | 220K |
REV. 0
–2–
AD7776/AD7777/AD7778–SPECIFICATIONS
CLKIN= 8 MHz; RTN= OV; C
REFIN
= 10 nF; all specifications T
MN
to T
MAX
unless otherwse noted.)
A Versions
1
CC
= +5 V
6
5%; AGND = DGND = OV;
Parameter
Units
Conditions/Comments
DC ACCURACY
Resolution
2
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
Bias Offset Error Match
Plus or Minus Full-Scale Error
Plus or Minus Full-Scale Error Match 10
10
±
1
±
1
±
12
10
±
12
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
See T erminology
No Missing Codes; See T erminology
See T erminology
Between Channels, AD7777/AD7778 Only; See T erminology
See T erminology
Between Channels, AD7777/AD7778 Only; See T erminology
ANALOG INPUT S
Input Voltage Range
All Inputs
Input Current
V
BIAS
±
V
SWING
+200
V min/V max
μ
A max
V
IN
= V
BIAS
±
V
SWING
; Any Channel
REFERENCE INPUT
REFIN
REFIN Input Current
1.9/2.1
+200
V min/V max
μ
A max
For Specified Performance
REFERENCE OUT PUT
REFOUT
DC Output Impedance
Reference Load Change
1.9/2.1
5
±
2
±
5
V min/V max
typ
mV max
mV max
Nominal REFOUT = 2.0 V
For Reference Load Current Change of 0 to
±
500
μ
A
For Reference Load Current Change of 0 to
±
1 mA
Reference Load Should Not Change During Conversion
See T erminology
Short Circuit Current
3
20
mA max
LOGIC OUT PUT S
DB0–DB9,
BUSY
/
INT
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Capacitance
3
ADC Output Coding
0.4
4.0
±
10
10
T wos Complement
V max
V min
μ
A max
pF max
I
SINK
= 1.6 mA
I
SOURCE
= 200
μ
A
LOGIC INPUT S
DB0–DB9,
CS
,
WR
,
RD
, CLK IN
Input Low Voltage, V
INL
Input High Voltage, V
INH
Input Leakage Current
Input Capacitance
3
0.8
2.4
10
10
V max
V min
μ
A max
pF max
CONVERSION T IMING
Acquisition T ime
4.5 t
CLK IN
5.5 t
CLK IN
+ 70
14 t
CLK IN
28 t
125/500
50
40
ns min
ns max
ns max
ns max
ns min/ns max Period of Input Clock CLK IN
ns min
Minimum High T ime for CLK IN
ns min
Minimum Low T ime for CLK IN
See T erminology
Single Conversion
Double Conversion
t
CLK IN
t
CLK IN
High
t
CLK IN
Low
POWER REQUIREMENT S
V
CC
Range
I
CC
, Normal Mode
I
, Power-Down Mode
Power-Up T ime to Operational
Specifications
+4.75/+5.25
15
1.5
V min/V max
mA max
mA max
For Specified Performance
CS
=
RD
= +5 V, CR8 = 0
CR8 = 1. All Linear Circuitry OFF
500
μ
s max
From Power-Down Mode
DYNAMIC PERFORMANCE
Signal to Noise and Distortion
S/(N+D) Ratio
T otal Harmonic Distortion (T HD)
Intermodulation Distortion (IMD)
See T erminology
–57
–60
–75
dB min
dB min
dB typ
V
IN
= 99.88 kHz Full-Scale Sine Wave with f
SAMPLING
= 380.95 kHz
V
IN
= 99.88 kHz Full-Scale Sine Wave with f
SAMPLING
= 380.95 kHz
fa = 103.2 kHz, fb = 96.5 kHz with f
SAMPLING
= 380.95 kHz. Both
Signals Are Sine Waves at Half-Scale Amplitude
V
IN
= 100 kHz Full-Scale Sine Wave with f
SAMPLING
= 380.95 kHz
Channel-to-Channel Isolation
–90
dB typ
NOT ES
1
T emperature range as follows: A = –40
°
C to +85
°
C.
2
1 LSB = (2
×
V
)/1024 = 1.95 mV for V
SWING
= 1.0 V.
3
Guaranteed by design, not production tested.
Specifications subject to change without notice.
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