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參數資料
| 型號： | AD7782 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Read Only, Pin Configured 24-Bit ADC |
| 中文描述： | 只讀，引腳配置24位ADC |
| 文件頁數： | 4/12頁 |
| 文件大小： | 126K |
| 代理商： | AD7782 |
REV. 0
–4–
TIMING CHARACTERISTICS
1, 2
(V
DD
= 2.7 V to 3.6 V or V
DD
= 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V,
Logic 1 = V
DD
unless otherwise noted.)
Limit at T
MIN
, T
MAX
(B Version)
Parameter
Unit
μ
s typ
ms typ
ns min
ns min
ns max
ns max
ns typ
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
Conditions/Comments
t
1
t
ADC
t
2
t
3
30.5176
50.54
0
0
60
80
2
×
t
ADC
0
60
80
10
80
0
10
80
Crystal Oscillator Period
19.79 Hz Update Rate
CH1
/CH2 Select to
CS
Setup Time
CS
Falling Edge to DOUT Active
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
Channel Settling Time
SCLK Active Edge to Data Valid Delay
4
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
Bus Relinquish Time after
CS
Inactive Edge
t
4
t
53
t
85
t
9
t
10
CS
Rising Edge to SCLK Inactive Edge Hold Time
SCLK Inactive to DOUT High
Slave Mode Timing
t
6
t
7
Master Mode Timing
t
6
t
7
t
11
100
100
ns min
ns min
SCLK High Pulsewidth
SCLK Low Pulsewidth
t
1
/2
t
1
/2
t
1
/2
3t
1
/2
μ
s typ
μ
s typ
μ
s min
μ
s max
SCLK High Pulsewidth
SCLK Low Pulsewidth
DOUT Low to First SCLK Active Edge
4
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part
and as such are independent of external bus loading capacitances.
TO OUTPUT
PIN
50pF
I
(1.6mA WITH V
DD
= 5V
100 A WITH V
DD
= 3V)
1.6V
I
(200 A WITH V
DD
= 5V
100 A WITH V
DD
= 3V)
Figure 1. Load Circuit for Timing Characterization
AD7782
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