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參數(shù)資料
| 型號： | AD7783 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Read-Only, Pin Configured 24-Bit ADC with Excitation Current Sources |
| 中文描述： | 只讀，引腳配置24位ADC的勵磁電流源 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 217K |
| 代理商： | AD7783 |
REV. B
AD7783
–9–
to the voltage on the AIN(
–
) input. For example, if AIN(
–
) is
2.5 V and the AD7783 is configured for an analog input range
of
±
160 mV, the analog input range on the AIN(+) input is
2.34 V to 2.66 V (i.e., 2.5 V
±
0.16 V).
The coding is offset binary with a negative full-scale voltage
resulting in a code of 000 . . . 000, a zero differential voltage
resulting in a code of 100 . . . 000, and a positive full-scale
voltage resulting in a code of 111 . . . 111. The output code for
any analog input voltage can be represented as follows:
(
where
AIN
is the analog input voltage,
GAIN
is the PGA gain,
i.e., 1 on the
±
2.56 V range and 16 on the
±
160 mV range,
and
N
= 24.
Excitation Currents
The AD7783 also contains two matched 200
m
A constant cur-
rent sources. Both source current from V
DD
that is directed to
either the IOUT1 or IOUT2 pins of the device depending on
the polarity of the IPIN pin. These current sources can be used
to excite external resistive bridge or RTD sensors.
Crystal Oscillator
The AD7783 is intended for use with a 32.768 kHz watch crys-
tal. A PLL internally locks onto a multiple of this frequency to
provide a stable 4.194304 MHz clock for the ADC. The modu-
lator sample rate is the same as the crystal oscillator frequency.
The start-up time associated with 32.768 kHz crystals is typically
300 ms. In some cases, it will be necessary to connect capacitors
on the crystal to ensure that it does not oscillate at overtones of
its fundamental operating frequency. The values of capacitors will
vary depending on the manufacturer
’
s specifications.
Reference Input
The AD7783 has a fully differential reference input capability
for the channel. The common-mode range for differential inputs
is from GND to V
DD
. The reference input is unbuffered, and
therefore excessive R-C source impedances will introduce gain
errors. The reference voltage REFIN (REFIN(+)
–
REFIN(
–
))
is 2.5 V nominal for specified operation, but the AD7783 is
functional with reference voltages from 1 V to V
DD
. In applica-
tions where the excitation (voltage or current) for the transducer
on the analog input also drives the reference voltage for the part,
the effect of the low frequency noise in the excitation source will
be removed as the application is ratiometric. If the AD7783 is
used in a nonratiometric application, a low noise reference should
be used. Recommended reference voltage sources for the AD7783
include the AD780, REF43, and REF192. It should also be noted
that the reference inputs provide a high impedance, dynamic load.
Because the input impedance of each reference input is dynamic,
resistor/capacitor combinations on these inputs can cause dc gain
errors, depending on the output impedance of the source that is
driving the reference inputs. Recommended reference voltage
sources (e.g., AD780) will typically have low output impedances
and are, therefore, tolerant to having decoupling capacitors
on the REFIN(+) without introducing gain errors in the system.
Code
AIN
GAIN
V
N
REF
=
￥
￥
￥
(
)
)
+
[
]
-
2
1 024
.
1
1
/
Deriving the reference input voltage across an external resistor
will mean that the reference input sees a significant external
source impedance. External decoupling on the REFIN pins
would not be recommended in this type of circuit configuration.
Grounding and Layout
Since the analog inputs and reference inputs on the ADC are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode rejection
of the part will remove common-mode noise on these inputs.
The digital filter will provide rejection of broadband noise on
the power supply, except at integer multiples of the modulator
sampling frequency. The digital filter also removes noise from
the analog and reference inputs, provided these noise sources do
not saturate the analog modulator. As a result, the AD7783 is
more immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD7783 is so high, and the noise levels from the AD7783 are so
low, care must be taken with regard to grounding and layout.
The printed circuit board that houses the AD7783 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. A minimum etch
technique is generally best for ground planes as it gives the best
shielding.
It is recommended that the AD7783
’
s GND pin be tied to the
AGND plane of the system. In any layout, it is important that
the user keep in mind the flow of currents in the system, ensur-
ing that the return paths for all currents are as close as possible
to the paths the currents took to reach their destinations. Avoid
forcing digital currents to flow through the AGND sections of
the layout.
The AD7783
’
s ground plane should be allowed to run under
the AD7783 to prevent noise coupling. The power supply lines
to the AD7783 should use as wide a trace as possible to provide
low impedance paths and reduce the effects of glitches on the
power supply line. Fast switching signals like clocks should be
shielded with digital ground to avoid radiating noise to other
sections of the board, and clock signals should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at
right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Good decoupling is important when using high resolution ADCs.
V
DD
should be decoupled with 10
m
F tantalum in parallel with
0.1
m
F capacitors to GND. To achieve the best from these
decoupling components, they have to be placed as close as pos-
sible to the device, ideally right up against the device. All
logic chips should be decoupled with 0.1
m
F ceramic capaci-
tors to DGND.
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