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參數(shù)資料
| 型號： | AD7841AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Octal 14-Bit, Parallel Input, Voltage-Output DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 31 us SETTLING TIME, 14-BIT DAC, PQFP44 |
| 封裝： | PLASTIC, MQFP-44 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 151K |
| 代理商： | AD7841AS |
AD7841
–5–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Description
1
DUTGND_AB
Device Sense Ground for DACs A and B. V
OUT
A and V
OUT
B are referenced to the voltage
applied to this pin.
DAC Outputs.
2, 32, 34,
35, 37, 41,
43, 44
3, 4
5, 38
6, 29
7
V
OUT
A . . V
OUT
H
V
REF
(–)AB, V
REF
(+)AB
V
DD
V
SS
LDAC
Reference Inputs for DACs A and B. These reference voltages are referred to GND.
Positive Analog Power Supply; +15 V
±
10% for Special Performance.
Negative Analog Power Supply; –15 V
±
10% for Special Performance.
Load DAC Logic Input (active low). When this logic input is taken low the contents of the
registers are transferred to their respective DAC registers.
LDAC
can be tied permanently
low enabling the outputs to be updated on the rising edge of
WR
.
Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a
data transfer.
Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
Level-Triggered Write Input (active low), used in conjunction with
CS
to write data to the
AD7841 data registers. Data is latched into the selected input register on the rising edge
of
WR
.
Logic Power Supply; +5 V
±
5%.
Ground.
Parallel Data Inputs. The AD7841 can accept a straight 14-bit parallel word on DB0 to
DB13 where DB13 is the MSB and DB0 is the LSB.
Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog
outputs are switched to the externally set potential on the relevant DUTGND pin. The con-
tents of input registers and DAC registers A to H are not affected when the
CLR
pin is taken
low. When
CLR
is brought back high, the DAC outputs revert to their original outputs as
determined by the data in their DAC registers.
Reference Inputs for DACs G and H. These reference voltages are referred to GND.
Device Sense Ground for DACs G and H. V
OUT
G and V
OUT
H are referenced to the voltage
applied to this pin.
Device Sense Ground for DACs E and F. V
OUT
E and V
OUT
F are referenced to the voltage
applied to this pin.
Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
Device Sense Ground for DACs C and D. V
OUT
C and V
OUT
D are referenced to the voltage
applied to this pin.
8, 9, 10
A2, A1, A0
11
12
CS
WR
13
14
15–28
V
CC
GND
DB0..DB12
29
CLR
30, 31
33
V
REF
(+)GH, V
REF
(–)GH
DUTGND_GH
36
DUTGND_EF
39
40
42
V
REF
(+)CDEF
V
REF
(–)CDEF
DUTGND_CD
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