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參數資料
| 型號： | AD7841BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Octal 14-Bit, Parallel Input, Voltage-Output DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 31 us SETTLING TIME, 14-BIT DAC, PQFP44 |
| 封裝： | PLASTIC, MQFP-44 |
| 文件頁數： | 3/12頁 |
| 文件大小： | 151K |
| 代理商： | AD7841BS |
–3–
REV. 0
AD7841
(These characteristics are included for Design Guidance and are not subject
to production testing.)
AC PERFORMANCE CHARACTERISTICS
A & B
Versions
Parameter
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
31
μ
s typ
Full-Scale Change to
±
1/2 LSB. DAC Latch Contents Alternately
Loaded with All 0s and All 1s
Slew Rate
Digital-to-Analog Glitch Impulse
0.7
230
V/
μ
s typ
nV-s typ
Measured with V
REF
(+) = +5 V, V
REF
(–) = –5 V. DAC Latch
Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent
on Load Conditions
See Terminology
See Terminology
Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Effect of Input Bus Activity on DAC Output Under Test
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
99
40
0.2
dB typ
nV-s typ
nV-s typ
Digital Feedthrough
Output Noise Spectral Density
@ 1 kHz
0.1
nV-s typ
200
nV/
√
Hz
typ
All 1s Loaded to DAC. V
REF
(+) = V
REF
(–) = 0 V
TIMING SPECIFICATIONS
1, 2
Parameter
Limit at T
MIN,
T
MAX
Units
Description
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
15
0
50
50
0
0
20
0
31
300
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μ
s typ
ns max
ns min
Address to
WR
Setup Time
Address to
WR
Hold Time
CS
Pulsewidth Low
WR
Pulsewidth Low
CS
to
WR
Setup Time
WR
to
CS
Hold Time
Data Setup Time
Data Hold Time
Settling Time
CLR
Pulse Activation Time
LDAC
Pulsewidth Low
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
t
1
t
2
t
5
t
6
t
3
t
4
t
7
t
8
t
9
t
10
t
11
LDAC
CLR
WR
CS
A0, A1, A2
DATA
V
OUT
V
OUT
Figure 1. Timing Diagram
(V
CC
= +5 V
6
5%; V
DD
= +15 V
6
10%; V
SS
= –15 V
6
10%; GND = DUTGND = 0 V)
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相關代理商/技術參數 |
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