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參數(shù)資料
| 型號： | AD7845KP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Complete 12-Bit Multiplying DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 12-BIT DAC, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 193K |
| 代理商： | AD7845KP |
AD7845
REV. B
–6–
PIN FUNCTION DESCRIPTION (DIP)
Pin
1
2-11
12
13-14
15
16
17
18
19
20
21
22
23
24
Mnemonic
V
OUT
DB11–DB2
DGND
DB1–DB0
WR
CS
V
REF
AGND
V
SS
V
DD
R
A
R
B
R
C
R
FB
Description
Voltage Output Terminal
Data Bit 11 (MSB) to Data Bit 2
Digital Ground. The metal lid on the ceramic package is connected to this pin
Data Bit 1 to Data Bit 0 (LSB)
Write Input. Active low
Chip Select Input. Active low
Reference Input Voltage which can be an ac or dc signal
Analog Ground. This is the reference point for external analog circuitry
Negative power supply for the output amplifier (nominal –12 V to +15 V)
Positive power supply (nominal +12 V to +15 V)
Application resistor. R
A
= 4 R
FB
Application resistor. R
B
= 2 R
FB
Application resistor. R
C
= 2 R
FB
Feedback resistor in the DAC. For normal operation this is connected to V
OUT
CIRCUIT INFORMATION
Digital Section
Figure 11 is a simplified circuit diagram of the AD7845 input
control logic. When
CS
and
WR
are both low, the DAC latch is
loaded with the data on the data inputs. All the digital inputs
are TTL, HCMOS and +5 V CMOS compatible, facilitating
easy microprocessor interfacing. All digital inputs incorporate
standard protection circuitry.
Figure 11. AD7845 Input Control Logic
D/A Section
Figure 12 shows a simplified circuit diagram for the AD7845
D/A section and output amplifier.
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. The
remaining 10 bits drive the switches (S0–S9) in a standard R-2R
ladder configuration.
R
R
R
2R
2R
2R
2R
2R
B
A
S9
2R
C
V
REF
S8
S0
SHOWN FOR ALL 1s ON DAC
2R
I
OUT
AGND
Figure 12. Simplified Circuit Diagram for the AD7845 D/A
Section
Each of the switches A–C steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.
An output amplifier and feedback resistor perform the current-
to-voltage conversion giving
V
OUT
= –
D
×
V
REF
where
D
is the fractional representation of the digital word. (
D
can be set from 0 to 4095/4096.)
The amplifier can maintain
±
10 V across a 2 k
load. It is inter-
nally compensated and settles to 0.01% FSR (1/2 LSB) in less
than 5
μ
s. The input offset voltage is laser trimmed at wafer
level. The amplifier slew rate is typically 11 V/
μ
s, and the unity
gain small signal bandwidth is 600 kHz. There are three extra
on-chip resistors (R
A
, R
B
, R
C
) connected to the amplifier invert-
ing terminal. These are useful in a number of applications in-
cluding offset adjustment and gain ranging.
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