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參數資料
| 型號： | AD7849AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Serial Input, 14-Bit/16-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 14-BIT DAC, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數： | 5/15頁 |
| 文件大小： | 211K |
| 代理商： | AD7849AR |
AD7849
REV. B
–5–
TERMINOLOGY
Least Significant Bit
This is the analog weighting of 1 bit of the digital word in a DAC.
For the AD7849, B, C and T versions, 1 LSB = (V
REF+
– V
REF–
)/
2
16
. For the AD7849, A version, 1 LSB = (V
REF+
– V
REF–
)/2
14
.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., offset and gain errors are ad-
justed out) and is normally expressed in least significant bits or
as a percentage of full-scale range.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of less than
±
1 LSB over the
operating temperature range ensures monotonicity.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer.
Offset Error
This is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
Bipolar Zero Error
When the AD7849 is connected for bipolar output and
(100 . . . 000) is loaded to the DAC, the deviation of the analog
output from the ideal midscale of 0 V, is called the bipolar zero
error.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is nor-
mally specified as the area of the glitch in nV-secs.
Multiplying Feedthrough Error
This is an ac error due to capacitive feedthrough from either of
the V
REF
terminals to V
OUT
when the DAC is loaded with all 0s.
Digital Feedthrough
When the DAC is not selected (
SYNC
is held high), high fre-
quency logic activity on the digital inputs is capacitively coupled
through the device to show up as noise on the V
OUT
pin. This
noise is digital feedthrough.
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
2
3
4
5
6
7
V
REF+
V
REF–
V
SS
SYNC
SCLK
V
CC
SDOUT
V
REF+
Input. The DAC is specified for V
REF+
of +5 V. The DAC is fully multiplying so that the V
REF+
range is +5 V to –5 V.
V
REF–
Input. The DAC is specified for V
REF–
of –5 V. Since the DAC is fully multiplying the V
REF–
range is –5 V to +5 V.
Negative supply for the analog circuitry. This is nominally –15 V.
Data Synchronization Logic Input. When it goes low, the internal logic is initialized in readiness for a new data word.
Serial Clock Logic Input. Data is clocked into the input register on each SCLK falling edge.
Positive supply for the digital circuitry. This is nominally +5 V.
Serial Data Output. With DCEN at Logic “1,” this output is enabled and the serial data in the input shift register is
clocked out on each rising edge of SCLK.
Daisy-Chain Enable Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise this pin must be
connect low.
Logic Input. This input selects the data format to be either binary or 2s complement. In the unipolar output range,
natural binary format is selected by connecting the input to a Logic “0.” In the bipolar output range, offset binary is
selected by connecting this input to a Logic “0” and 2s complement is selected by connecting it to a Logic “1.”
Digital Ground. Ground reference point for the on-chip digital circuitry.
Load DAC Logic Input. This input updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively, if this input is permanently low, an automatic update mode is selected whereby the DAC is updated
on the 16th falling SCLK edge.
Serial Data Input. The 16-bit serial data word is applied to this input.
Clear Logic Input. Taking this input low sets V
OUT
to 0 V in both the unipolar output range and the bipolar 2s comple-
ment output range. It sets V
OUT
to V
REF–
in the offset binary bipolar output range.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic “0” to this input, resets
the DAC output to 0 V. In normal operation it should be tied to Logic “1.”
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. It may used to control
other system components if desired.
This is the analog ground for the device. It is the point to which the output gets shorted in the reset mode.
Positive supply for the analog circuitry. This is +15 V nominal.
No Connect. Leave unconnected.
DAC Output Voltage Pin.
Input to summing resistor of DAC output amplifier. This is used to select output voltage ranges. See Figures 16 to 19
in “APPLYING THE AD7849.”
8
DCEN
9
BIN
/COMP
10
11
DGND
LDAC
12
13
SDIN
CLR
14
RSTIN
15
RSTOUT
16
17
18
19
20
AGND
V
DD
NC
V
OUT
R
OFS
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