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參數資料
| 型號： | AD7849CR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Serial Input, 14-Bit/16-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 16-BIT DAC, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數： | 11/15頁 |
| 文件大小： | 211K |
| 代理商： | AD7849CR |
AD7849
REV. B
–
11
–
Unipolar Configuration
Figure 16 shows the AD7849 in the unipolar binary circuit con-
figuration. The DAC is driven by the AD586, +5 V reference.
Since R
OFS
is tied to 0 V, the output amplifier has a gain of
×
2
and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, R
OFS
should be tied to V
OUT
, configuring the output
stage for a gain of
×
1. Table I gives the code table for the circuit
of Figure 16.
+15V
+5V
V
DD
V
CC
V
REF+
V
OUT
R
OFS
V
OUT
(0 TO +10V)
AGND
DGND
V
REF
–
V
SS
–
15V
AD7849*
R1
10k
AD586
C1
1nF
SIGNAL GND
6
8
4
5
*
ADDITIONAL PINS
OMITTED FOR CLARITY
2
Figure 16. Unipolar Binary Operation
Table I. Code Table for Figure 16
Binary Number in DAC Latch
MSB LSB
Analog Output
(V
OUT
)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
+10 (65535/65536) V
+10 (32768/65536) V
+10 (1/65536) V
0 V
NOTE: Assumes 16-bit resolution; 1 LSB = 10 V/2
16
= 10 V/65536 = 152
μ
V.
Offset and gain may be adjusted in Figure 16 as follows: To ad-
just offset, disconnect the V
REF–
input from 0 V, load the DAC
with all 0s and adjust the V
REF–
voltage until V
OUT
= 0 V. For
gain adjustment, the AD7849 should be loaded with all 1s and
R1 adjusted until V
OUT
= 10 (65535)/65536 = 9.9998474 V,
(B, T and C, 16-bit versions). For the 14-bit A version, V
OUT
should be 10 (16383/16384) = 9.9993896 V.
If a simple resistor divider is used to vary the V
REF–
voltage, it is
important that the temperature coefficients of these resistors match
that of the DAC input resistance (–300 ppm/
°
C). Otherwise, extra
offset errors will be introduced over temperature. Many circuits
will not require these offset and gain adjustments. In these cir-
cuits, R1
,
can be omitted. Pin 5 of the AD586 may be left open
circuit and Pin 2 (V
REF–
) of the AD7849 tied to 0 V.
Bipolar Configuration
Figure 17 shows the AD7849 set up for
±
10 V bipolar opera-
tion. The AD588 provides precision
±
5 V tracking outputs
which are fed to the V
REF+
and V
REF–
inputs of the AD7849.
The code table for Figure 17 is shown in Table II.
Full-scale and bipolar-zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588 while R3 adjusts the +5 V and –5 V outputs together
with respect to ground.
V
(
–
10V TO +10V)
+15V
+5V
V
DD
V
CC
V
OUT
V
REF+
R
OFS
AGND
DGND
V
REF
–
V
SS
–
15V
AD7849*
SIGNAL
GND
*
ADDITIONAL PINS
OMITTED FOR CLARITY
AD588
1C1
R2
100k
R3
100k
R1
39k
6
15
2
8
5
14
7
9
3
1
10
12
11
4
13
16
Figure 17. Bipolar
±
10 V Operation
Table II. Offset Binary Code Table for Figure 17
Binary Number in DAC Latch
MSB LSB
Analog Output
(V
OUT
)
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+10 (32767/32768) V
+10 (1/32768) V
0 V
–10 (1/32768) V
–10 (32768/32768) V
NOTE: Assumes 16-bit resolution; 1 LSB = 20 V/2
16
= 305
μ
V.
For bipolar-zero adjustment on the AD7849, load the DAC
with 100 . . . 000 and adjust R3 until V
OUT
= 0 V. Full scale is
adjusted by loading the DAC with all 1s and adjusting R2 until
V
OUT
= 9.999694 V.
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted, Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
If a user wants a
±
5 V output range with the circuit of Figure
17, simply tie Pin 20 (R
OFS
) to Pin 19 (V
OUT
), thus reducing the
output gain stage to unity and giving an output range of
±
5 V.
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