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參數資料
| 型號： | AD7854LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數： | 21/28頁 |
| 文件大小： | 264K |
| 代理商： | AD7854LAR |
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AD7854/AD7854L
REV. B
–
21
–
Self-Calibration Timing
Figure 29 shows the timing for a software full self-calibration.
Here the BUSY line stays high for the full length of the self-
calibration. A self-calibration is initiated by writing to the con-
trol register and setting the STCAL bit to 1. The BUSY line
goes high at the end of the write to the control register, and
BUSY goes low when the full self-calibration is complete after a
time t
CAL
as show in Figure 29.
t
23
DATA LATCHED INTO
CONTROL REGISTER
Hi-Z
Hi-Z
DATA
VALID
t
CAL
CS
WR
DATA
BUSY
Figure 29. Timing Diagram for Full Self-Calibration
For the self-(gain + offset), self-offset and self-gain calibrations,
the BUSY line is triggered high at the end of the write to the
control register and stays high for the full duration of the self-
calibration. The length of time for which BUSY is high depends
on the type of self-calibration that is initiated. Typical values are
given in Table VIII. The timing diagram for the other self-
calibration options is similar to that outlined in Figure 29.
System Calibration Description
System calibration allows the user to remove system errors
external to the AD7854/AD7854L, as well as remove the errors
of the AD7854/AD7854L itself. The maximum calibration
range for the system offset errors is
±
5% of V
REF
, and for the
system gain errors it is
±
2.5% of V
REF
. If the system offset or
system gain errors are outside these ranges, the system calibration
algorithm reduces the errors as much as the trim range allows.
Figures 30 through 32 illustrate why a specific type of system
calibration might be used. Figure 30 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be removed by a system offset calibration.
MAX SYSTEM OFFSET
IS ±5% OF V
REF
ANALOG
INPUT
RANGE
SYSTEM OFFSET
CALIBRATION
SYS OFFSET
AGND
V
REF
+ SYS OFFSET
V
REF
–
1LSB
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
ANALOG
INPUT
RANGE
MAX SYSTEM OFFSET
IS ±5% OF V
REF
V
REF
–
1LSB
SYS OFFSET
AGND
Figure 30. System Offset Calibration
Figure 31 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
ANALOG
INPUT
RANGE
SYSTEM OFFSET
CALIBRATION
AGND
SYS FULL S.
V
REF
–
1LSB
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
–
1LSB
SYS FULL S.
AGND
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
Figure 31. System Gain Calibration
Finally in Figure 32 both the system offset error and gain error
are removed by the system offset followed by a system gain cali-
bration. First the analog input range is shifted upwards by the
positive system offset and then the analog input range is
adjusted at the top end to account for the system full scale.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
MAX SYSTEM OFFSET
IS ±5% OF V
REF
ANALOG
INPUT
RANGE
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
SYSTEM GAIN
CALIBRATIONSYS OFFSET
AGND
V
REF
+ SYS OFFSET
V
REF
–
1LSB
ANALOG
INPUT
RANGE
MAX SYSTEM OFFSET
IS ±5% OF V
REF
V
REF
–
1LSB
SYS OFFSET
AGND
SYS F.S.
SYS F.S.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
Figure 32. System (Gain + Offset) Calibration
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| AD7854LARSZ | 功能描述:IC ADC 12BIT PARALLEL LP 28SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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