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參數資料
| 型號： | AD7863ARS-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Simultaneous Sampling Dual 175 kSPS 14-Bit ADC |
| 中文描述： | 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MO-150AH, SSOP-28 |
| 文件頁數： | 3/18頁 |
| 文件大小： | 207K |
| 代理商： | AD7863ARS-3 |
AD7863
–3–
REV. A
A
Version
1
B
Version
1
Parameter
Units
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB11
–
DB0
Floating-State Leakage Current
Floating-State Capacitance
5
Output Coding
AD7863-10, AD7863-3
AD7863-2
CONVERSION RATE
Conversion Time
Mode 1 Operation
Mode 2 Operation
6
Track/Hold Acquisition Time
4, 7
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Mode 1)
AD7863-10
AD7863-3
AD7863-2
Power-Down Mode (Mode 2)
I
DD
@ +25
°
C
8
Power Dissipation
Normal Mode (Mode 1)
AD7863-10
AD7863-3
AD7863-2
Power-Down Mode @ +25
°
C
4.0
0.4
4.0
0.4
V min
V max
I
SOURCE
= 200
μ
A
I
SINK
= 1.6 mA
±
10
10
±
10
10
μ
A max
pF max
Twos Complement
Straight (Natural) Binary
5.2
10.0
0.5
5.2
10.0
0.5
μ
s max
μ
s max
μ
s max
For Both Channels
For Both Channels
+5
+5
V nom
±
5% for Specified Performance
17
15
10
17
15
10
mA max
mA max
mA max
20
20
μ
A max
40 nA typ. Logic Inputs = 0 V or V
DD
89.25
78.75
52.5
105
89.25
78.75
52.5
105
mW max
mW max
mW max
μ
W max
V
DD
= 5.25 V, Typically 70 mW
V
DD
= 5.25 V, Typically 70 mW
V
DD
= 5.25 V, Typically 45 mW
Typically 210 nW, V
DD
= 5.25 V
NOTES
1
Temperature ranges are as follows: A, B Versions:
–
40
°
C to +85
°
C.
2
Sample tested during initial release.
3
Applies to Mode 1 operation. See section on operating modes.
4
See Terminology.
5
Sample tested @ +25
°
C to ensure compliance.
6
This 10
μ
s includes the
“
wake-up
”
time from standby. This
“
wake-up
”
time is timed from the rising edge of
CONVST
, whereas conversion is timed from the falling
edge of
CONVST
, for a narrow
CONVST
pulsewidth the conversion time is effectively the
“
wake-up
”
time plus conversion time, hence 10
μ
s. This can be seen from
Figure 6. Note that if the
CONVST
pulsewidth is greater than 5.2
μ
s, the effective conversion time will increase beyond 10
μ
s.
7
Performance measured through full channel (multiplexer, SHA and ADC).
8
For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of
operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore the 40 nA typical figure shown
is a characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The max figure shown in the Conditions/
Comments column reflects the AD7863 with supply decoupling in place
—
0.1
μ
F in parallel with a 10
μ
F disc ceramic capacitors on the V
DD
pin and 2
×
0.1
μ
F disc
ceramic capacitors on the V
REF
pin, in both cases to the AGND plane.
Specifications subject to change without notice.
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