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參數資料
| 型號： | AD7866 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface |
| 中文描述： | 雙1 MSPS的12位，雙通道SAR型ADC的串行接口 |
| 文件頁數： | 14/20頁 |
| 文件大?。?/td> | 304K |
| 代理商： | AD7866 |
REV. 0
AD7866
–14–
100nF
2.5V
REF
ADC B
EXT REF
EXT REF
470nF
D
CAP
B
D
CAP
A
V
REF
EXT REF
470nF
BUF B
ADC A
BUF A
Figure 15. Reference Circuit
be taken from either the V
REF
pin or one of the D
CAP
A or D
CAP
B
pins. If it is taken from the V
REF
pin, it must be buffered before
being applied elsewhere as it will not be capable of sourcing more
than a few microamps. If the reference voltage is taken from
either the D
CAP
A pin or D
CAP
B pin, a buffer is not strictly neces-
sary. Either pin is capable of sourcing current in the region of
100
μ
A; however, the larger the source current requirement, the
greater the voltage drop seen at the pin. The output impedance of
each of these pins is typically 50
. In addition, this point repre-
sents the actual voltage applied to the ADC internally so any
voltage drop due to the current load or disturbance due to a
dynamic load will directly affect the ADC conversion. For
this reason, if a large current source is necessary, or a dynamic
load is present, it is recommended to use a buffer on the output
to drive a device.
Examples of suitable external reference devices that may be
applied at pins V
REF
, D
CAP
A, or D
CAP
B are the AD780, REF192,
REF43, or AD1582.
MODES OF OPERATION
The mode of operation of the AD7866 is selected by controlling
the (logic) state of the
CS
signal during a conversion. There
are three possible modes of operation, Normal Mode, Partial
Power-Down Mode, and Full Power-Down Mode. The point at
which
CS
is pulled high after the conversion has been initiated
will determine which power-down mode, if any, the device will
enter. Similarly, if already in a power-down mode,
CS
can
control whether the device will return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance as
the user does not have to worry about any power-up times with
the AD7866 remaining fully powered all the time. Figure 16 shows
the general diagram of the operation of the AD7866 in this mode.
The conversion is initiated on the falling edge of
CS
as described in
the Serial Interface section. To ensure the part remains fully pow-
ered up at all times
CS
must remain low until at least 10 SCLK
falling edges have elapsed after the falling edge of
CS
. If
CS
is
brought high any time after the 10th SCLK falling edge, but before
the 16th SCLK falling edge, the part will remain powered up but
the conversion will be terminated and D
OUT
A and D
OUT
B will go
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the conversion result. The
D
OUT
line will not return to three-state after 16 SCLK cycles have
elapsed, but instead when
CS
is brought high again. If
CS
is left
low for a further 16 SCLK cycles then the result from the other
ADC on board will also be accessed on the same D
OUT
line as
shown in Figure 22 (see Serial Interface section). The STATUS
bits provided prior to each conversion result will identify which
ADC the following result will be from. Once 32 SCLK cycles
have elapsed, the D
OUT
line will return to three-state on the 32nd
SCLK falling edge. If
CS
is brought high prior to this, the D
OUT
line
will return to three-state at that point. Hence,
CS
may idle low after
32 SCLK cycles, until it is brought high again sometime prior to the
next conversion (effectively idling
CS
low), if so desired, as the bus
will still return to three-state upon completion of the dual result read.
Once a data transfer is complete and D
OUT
A and D
OUT
B have
returned to three-state, another conversion can be initiated after
the quiet time, t
QUIET
, has elapsed by bringing
CS
low again.
Partial Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be per-
formed at a high throughput rate and the ADC is then powered
down for a relatively long duration between these bursts of several
conversions. When the AD7866 is in Partial Power-Down, all
analog circuitry is powered down except for the on-chip reference
and reference buffer.
SCLK
D
OUT
A
D
OUT
B
CS
STATUS BITS AND CONVERSION RESULT
1
16
10
Figure 16. Normal Mode Operation
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