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參數(shù)資料
| 型號： | AD7866BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大小： | 304K |
| 代理商： | AD7866BRU |
REV. 0
–20–
C
P
AD7866
shielding. Both AGND pins of the AD7866 should be sunk in the
AGND plane. Digital and analog ground planes should be joined
at only one place. If the AD7866 is in a system where multiple
devices require an AGND-to-DGND connection, the connection
should still be made at one point only, a star ground point that
should be established as close as possible to the AD7866.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7866 to avoid noise coupling. The power
supply lines to the AD7866 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with 10
μ
F tantalum in parallel with 0.1
μ
F capacitors
to AGND. All digital supplies should have at least a 0.1
μ
F disc
ceramic capacitor to DGND. V
DRIVE
should have a 0.1
μ
F ceramic
capacitor to DGND. To achieve the best from these decoupling
components, they must be placed as close as possible to the device,
ideally right up against the device. The 0.1
μ
F capacitors should
have low Effective Series Resistance (ESR) and Effective Series
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Thin Shrink Small Outline Package
(RU-20)
20
1
11
10
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.006 (0.15)
0.002 (0.05)
0.260 (6.60)
0.252 (6.40)
SEATING
PLANE
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
Inductance (ESI), such as common ceramic or surface mount types,
which provide a low
impedance path to ground at high frequen-
cies to handle transient
currents due to internal logic switching.
Figure 27 shows the recommended supply decoupling scheme.
For information on the decoupling requirements of each reference
configuration, see the Reference section.
AGND
DGND
AD7866
DV
DD
AV
DD
0.1 F
10 F
AGND
0.1 F
10 F
V
DRIVE
0.1 F
Figure 27. Recommended Supply Decoupling Scheme
Evaluating the AD7866 Performance
The recommended layout for the AD7866 is outlined in the evalu-
ation board for the AD7866. The evaluation board package includes
a fully assembled and tested evaluation board, documentation, and
software for controlling the board from the PC via the EVAL-
BOARD CONTROLLER. The EVAL-BOARD CONTROLLER
can be used in conjunction with the AD7866 Evaluation board, as
well as many other Analog Devices evaluation boards ending in the
CB designator, to demonstrate/evaluate the ac and dc performance
of the AD7866.
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7866.
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