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參數(shù)資料
型號(hào): AD7873
廠商: Analog Devices, Inc.
英文描述: Touch Screen Digitizer
中文描述: 觸摸屏數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 14/28頁(yè)
文件大小: 657K
代理商: AD7873
AD7873
ANALOG INPUT
Figure 26 shows an equivalent circuit of the analog input
structure of the AD7873, which contains a block diagram of the
input multiplexer, the differential input of the ADC, and the
differential reference.
Rev. D | Page 14 of 28
Table 5 shows the multiplexer address corresponding to each
analog input, both for the SER/DFR bit in the control register
set high and low. The control bits are provided serially to the
device via the DIN pin. For more information on the control
register, see the Control Register section.
When the converter enters hold mode, the voltage difference
between the +IN and –IN inputs (see Figure 26) is captured on
the internal capacitor array. The input current on the analog
inputs depends on the conversion rate of the device. During the
sample period, the source must charge the internal sampling
capacitor (typically 37 pF). Once the capacitor is fully charged,
there is no further input current. The rate of charge transfer
from the analog source to the converter is a function of
conversion rate.
0
X+ Y+
REF
INT/
EXT
X– Y– GND
6-TO-1
MUX
3-TO-1
MUX
3-TO-1
MUX
IN+
IN+
IN– REF–
REF+
ADC CORE
DATA OUT
V
CC
Y–
Y+
X+
X–
ON-CHIP SWITCHES
X+
Y+
Y–
V
BAT
AUX
TEMP
Figure 26. Equivalent Analog Input Circuit
Table 5. Analog Input, Reference, and Touch Screen Control
A2
A1
A0
SER/ DFR
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
Analog Input
TEMP0
X+
VBAT
X+ (Z1)
Y– (Z2)
Y+
AUX
TEMP1
Invalid Address. Test Mode: Switches out the Temp0 diode to the PENIRQ pin.
X+
OFF
Invalid Address
X+ (Z1)
X+ OFF
X– ON
Y– (Z2)
X+ OFF
X– ON
Y+
ON
Outputs Identity Code, 1000 0000 0000.
Invalid address. Test mode: Switches out the Temp1 diode to the PENIRQ pin.
X Switches
OFF
OFF
OFF
X+ OFF
X– ON
X+ OFF
X– ON
ON
OFF
OFF
Y Switches
OFF
ON
OFF
Y+ ON
Y– OFF
Y+ ON
Y– OFF
OFF
OFF
OFF
+REF
1
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
–REF
1
GND
GND
GND
GND
GND
GND
GND
GND
ON
Y+
Y–
Y+ ON
Y– OFF
Y+ ON
Y– OFF
OFF
Y+
Y+
X+
X–
X–
X–
1
Internal node, not directly accessible by the user.
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