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參數(shù)資料
| 型號(hào)： | AD7880CQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Enclosed Switches Series LS: Wobble - Steel Wire; 1NC 1NO DPDT Snap Action, Double Break; 0.5 in - 14NPT conduit; Plug-in |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大小： | 337K |
| 代理商： | AD7880CQ |
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AD7880
–10–
REV. 0
a write operation starts a conversion. Data is read at the end of
the conversion sequence as before. Figure 19 shows an example
of initiating conversion using this method. A similar implemen-
tation can be used for DSPs. Note that for all interfaces, a read
operation should not be attempted during conversion.
AD7880–MC68000 Interface
An interface between the AD7880 and the MC68000 is shown
in Figure 18. As before, conversion is initiated using an external
timer. T he AD7880
BUSY
line can be used to interrupt the
processor or, alternatively, software delays can ensure that con-
version has been completed before a read to the AD7880 is at-
tempted. Because of the nature of its interrupts, the 68000
requires additional logic (not shown in Figure 18) to allow it to
be interrupted correctly. For further information on 68000 in-
terrupts, consult the 68000 users manual.
T he MC68000
AS
and R/
W
outputs are used to generate a
separate
RD
input signal for the AD7880.
CS
is used to drive
the 68000
DTACK
input to allow the processor to execute a
normal read operation to the AD7880. T he conversion results
are read using the following 68000 instruction:
MOVE.W ADC, D
0
where
D
0
is the 68000 D0 register
where
ADC
is
the AD7880 address
A0
A15
D15
D0
ADDR
DECODE
ADDRESS BUS
DATA BUS
CONVST
CS
A
RD
AD7880*
MC68000
*ADDITIONAL PINS OMITTED FOR CLARITY
R/W
AS
EN
DTACK
TIMER
A
Figure 18. AD7880–MC68000 Interface
AD7880–8086 Interface
Figure 19 shows an interface between the AD7880 and the
8086 microprocessor. Unlike the previous interface examples,
the microprocessor initiates conversion. T his is achieved by gat-
ing the 8086
WR
signal with a decoded address output (differ-
ent to the AD7880
CS
address). Conversion is initiated and the
result is read from the AD7880 using the following instruction:
MOV AX , ADC
where
AX
is
the 8086 accumulator and
where
ADC
is
the AD7880 address
AD15
AD0
ADDR
DECODE
ADDRESS BUS
ADDRESS/DATA BUS
CONVST
CS
A
RD
AD7880*
8086
*ADDITIONAL PINS OMITTED FOR CLARITY
WR
RD
LATCH
ALE
Figure 19. AD7880–8086 Interface
AD7880–6809 Interface
T he AD7880 can also interface quite easily with 8-bit micro-
processors. T he 12-bit parallel data output from the AD7880
can be read into the microprocessor as an 8+4 byte structure.
Figure 20 shows an interface to the MC6809 8-bit microproces-
sor. As in previous cases, conversion is initiated using an exter-
nal timer. At the end of conversion,
BUSY
triggers a one-shot
which drives the
IRQ
interrupt input of the microprocessor. A
double read is then performed to two unique addresses. T he
first read fetches the lower 8 bits (DB0–DB7) and loads the
74HC374 latch with the upper 4 bits (DB8–DB11). T he sec-
ond read fetches these upper 4 bits.
A0
A15
D7
D0
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB7
A
DB0
RD
AD7880*
MC6809
*ADDITIONAL PINS OMITTED FOR CLARITY
R/W
IRQ
E
BUSY
A
ONE
SHOT
Q3
Q0
74HC374
CLK
D3
D0
OE
DB8
DB11
A
Figure 20. AD7880–6809 Interface
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