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參數(shù)資料
| 型號： | AD7880CQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Enclosed Switches Series LS: Wobble - Steel Wire; 1NC 1NO DPDT Snap Action, Double Break; 0.5 in - 14NPT conduit; Plug-in |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 337K |
| 代理商： | AD7880CQ |
AD7880
REV. 0
–9–
MICROPROCE SSOR INT E RFACING
T he AD7880 high speed bus timing allows direct interfacing to
real time digital signal processors, DSPs, as well as modern high
speed, 16-bit microprocessors. Suitable microprocessor inter-
faces are shown in Figures 15 through 20.
AD7880–ADSP-2100 Interface
Figure 15 shows an interface between the AD7880 and the
ADSP-2100. Conversion is initiated using a timer to drive the
CONVST
input asynchronously to the microprocessor. T his al-
lows very accurate control of the sampling instant. When con-
version is complete, the AD7880
BUSY
line goes high. An
inverter on this
BUSY
output drives the
IRQ
line low thus pro-
viding an interrupt to the ADSP-2100 when conversion is com-
pleted. T he conversion result is then read from the AD7880 into
the ADSP-2100 with the following instruction:
MR0 = DM(ADC)
where
MR0
is
the ADSP-2100 MR0 Register and
where
ADC
is the AD7880 address.
TIMER
DMA0
DMA13
DMD15
DMD0
DMS
EN
ADDR
DECODE
ADDRESS BUS
ADSP-2100
(ADSP-2101/
ADSP-2102)
* ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
CONVST
CS
A
RD
BUSY
AD7880*
IRQn
DMRD (RD)
A
Figure 15. AD7880–ADSP-2100 (ADSP-2101/ADSP-2102)
Interface
AD7880-ADSP-2101/ADSP-2102 Interface
T he interface outlined in Figure 15 also forms the basis for an
interface between the AD7880 and the ADSP-2101/ADSP-2102.
T he READ line of the ADSP-2101/ADSP-2102 is labeled
RD
.
In this interface, the
RD
pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. T he instruction used to read a conversion result is as out-
lined for the ADSP-2100.
AD7880-T MS32010 Interface
An interface between the AD7880 and the T MS32010 is shown
in Figure 16. Once again the conversion is initiated using an ex-
ternal timer and the T MS32010 is interrupted when conversion
is completed. T he following instruction is used to read the con-
version result from the AD7880:
IN D,ADC
where
D
is
Data Memory Address and
where
ADC
is the AD7880 address.
PA0
PA2
D15
D0
MEN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
A
RD
AD7880*
TMS32010
*ADDITIONAL PINS OMITTED FOR CLARITY
INT
DEN
EN
BUSY
A
Figure 16. AD7880–TMS32010 Interface
AD7880–T MS320C25 Interface
Figure 17 shows an interface between the AD7880 and the
T MS320C25. As with the two previous interfaces, conversion is
initiated with a timer, and the processor is interrupted when the
conversion sequence is completed. T he T MS320C25 does not
have a separate
RD
output to drive the AD7880
RD
input di-
rectly. T his has to be generated from the processor
STRB
and
R/
W
outputs with the addition of some logic gates. T he
RD
sig-
nal is OR-gated with the
MSC
signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7880 using the follow-
ing instruction:
IN D,ADC
where
D
is
Data Memory Address and
where
ADC
is the AD7880 address.
A0
A15
D15
D0
IS
EN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
AD7880*
TMS320C25
*ADDITIONAL PINS OMITTED FOR CLARITY
INTn
R/W
STRB
MSC
READY
BUSY
Figure 17. AD7880–TMS320C25 Interface
Some applications may require that the conversion be initiated
by the microprocessor rather than an external timer. One option
is to decode the AD7880
CONVST
from the address bus so that
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